count_6.vhd

来自「多功能秒表的设计」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count_6 IS
  PORT(clk,clr: IN STD_LOGIC;
       co:OUT STD_LOGIC;
       qout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END count_6;
ARCHITECTURE behave OF count_6 IS
    SIGNAL coun_6:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
    PROCESS(clk,clr)
   BEGIN
     IF(clr='1') THEN 
            coun_6<=(OTHERS=>'0');
     ELSIF(clk'EVENT AND clk='1')THEN 
        co<='0';
        IF (coun_6=5) THEN 
              coun_6<="0000";
			  co<='1';
        ELSIF(coun_6<5) THEN
			coun_6<=coun_6+1;
		END IF;
     END IF;
  END PROCESS;
 qout<=coun_6;
END behave;