bcd_decoder.vhd

来自「多功能秒表的设计」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bcd_decoder IS
  PORT (din: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        y: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END bcd_decoder;
ARCHITECTURE behave OF bcd_decoder IS
SIGNAL indata:  STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 
   indata<=din;
PROCESS(indata)
   BEGIN
       CASE indata IS
           WHEN "0000"=>y<="1111110";
           WHEN "0001"=>y<="0110000";
           WHEN "0010"=>y<="1101101";
           WHEN "0011"=>y<="1111001";
           WHEN "0100"=>y<="0110011";
           WHEN "0101"=>y<="1011011";
           WHEN "0110"=>y<="1011111";
           WHEN "0111"=>y<="1110000";
           WHEN "1000"=>y<="1111111";
           WHEN "1001"=>y<="1111011";
		   WHEN OTHERS=>y<="0000000";
       END CASE;
   END PROCESS;
END behave;