mux_6_1.vhd

来自「多功能秒表的设计」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*****************************************
ENTITY mux_6_1 IS
  PORT
   ( data_smin: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 data_gmin: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 data_ssec: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 data_gsec: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 data_smm: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  	 data_gmm: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 count_flag:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	 bcd_out:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0)	
	);
END mux_6_1;
--*****************************************
ARCHITECTURE behave OF mux_6_1 IS
   BEGIN
	bcd_out<=data_gmm WHEN count_flag=0 ELSE
			data_smm WHEN count_flag=1 ELSE
			data_gsec WHEN count_flag=2 ELSE
			data_ssec WHEN count_flag=3 ELSE
			data_gmin WHEN count_flag=4 ELSE
			data_smin WHEN count_flag=5 ELSE
 		    "1111";
END behave;