exchange_ctl.vhd

时钟分配和分路传输功能的VHDL语言程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity exchange_ctl is
    Port (
		CLK_100M : in std_logic;--100M : dsp clk out
		TA_IN : in std_logic_vector(2 downto 0);
		RA_IN : in std_logic_vector(2 downto 0);
		EN_S_MODEL: in std_logic;--active '1'
		EN_T_MODEL : in STD_LOGIC;
		CLR : in std_logic;--active '1'	
		ST : in std_logic;	
		WE : in std_logic;
		CTL_A : out std_logic_vector(3 downto 0);
		CTL_B : out std_logic_vector(3 downto 0);
		CTL_C : out std_logic_vector(3 downto 0);
		CTL_D : out std_logic_vector(3 downto 0);
		CTL_E : out std_logic_vector(3 downto 0)
    
     );
end exchange_ctl;

architecture a of exchange_ctl is
component pcmctl_ram_ctl
	port (
		CLK: in STD_LOGIC; --100M : dsp clk out
		CLR: in STD_LOGIC;
		EN_S_MODEL : in STD_LOGIC;
		EN_T_MODEL : in STD_LOGIC;
		RA: in STD_LOGIC_VECTOR (2 downto 0);
		TA: in STD_LOGIC_VECTOR (2 downto 0);
		WE: in STD_LOGIC;
		CTL_RAM_WE: out STD_LOGIC;
		D_USER: out STD_LOGIC_VECTOR (2 downto 0);
		S_USER: out STD_LOGIC_VECTOR (2 downto 0));
end component ;


signal TA,RA,S_USER,D_USER : std_logic_vector(2 downto 0);
signal CTL_RAM_WE : std_logic;
signal CTL_A_TMP,CTL_B_TMP,CTL_D_TMP,CTL_E_TMP,CTL_C_TMP : std_logic_vector(3 downto 0);
begin

CTL_A<=CTL_A_TMP;
CTL_B<=CTL_B_TMP;
CTL_C<=CTL_C_TMP;
CTL_D<=CTL_D_TMP;
CTL_E<=CTL_E_TMP;
TA <= TA_IN;
RA <= RA_IN;
INSERT_CTLRAM: pcmctl_ram_ctl
port map(
		CLK => CLK_100M,
		CLR => CLR,
		EN_S_MODEL => EN_S_MODEL,
		EN_T_MODEL => EN_T_MODEL,
		RA => RA,
		TA => TA,
		WE => WE,
		CTL_RAM_WE => CTL_RAM_WE,
		D_USER => D_USER,
		S_USER => S_USER);

EXCHANGE_A:process(CTL_RAM_WE,CLR,S_USER,CLK_100M)
begin 				   
	if CLR ='1' then
		CTL_A_TMP<="0000";
		CTL_B_TMP<="0000";
		CTL_C_TMP<="0000";
		CTL_D_TMP<="0000";
		CTL_E_TMP<="0000";
	elsif rising_edge(CLK_100M) then
		if S_USER ="000" and CTL_RAM_WE='0' then
			CTL_A_TMP<= ST&D_USER;
		else
			CTL_A_TMP<=CTL_A_TMP;
		end if;
		if S_USER ="001" and CTL_RAM_WE='0' then
			CTL_B_TMP<= ST&D_USER;
		else
			CTL_B_TMP<=CTL_B_TMP;
		end if;	
		if S_USER ="010" and CTL_RAM_WE='0' then
			CTL_C_TMP<= ST&D_USER;
		else
			CTL_C_TMP<=CTL_C_TMP;
		end if;
		if S_USER ="011" and CTL_RAM_WE='0' then
			CTL_D_TMP<= ST&D_USER;
		else
			CTL_D_TMP<=CTL_D_TMP;
		end if;
		if S_USER ="100" and CTL_RAM_WE='0' then
			CTL_E_TMP<= ST&D_USER;
		else
			CTL_E_TMP<=CTL_E_TMP;
		end if;
	end if;	 
end process	EXCHANGE_A;
end a;