dff.vhd

来自「时钟分配和分路传输功能的VHDL语言程序」· VHDL 代码 · 共 51 行

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--
-- Title       : dff
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
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--
-- File        : dff.vhd
-- Generated   : Tue Nov  4 13:37:53 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {da_control} architecture {arch}}
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DFF is
    Port (CLK,RESET,DIN: in std_logic;
    		DOUT: out std_logic );
end DFF;

architecture Behavioral of DFF is

begin
process (CLK, RESET)
begin
   if RESET='0' then   --asynchronous RESET active High
      DOUT <= '0';
   elsif (CLK'event and CLK='1') then  --CLK rising edge
      DOUT <= DIN;
   end if;
end process;
end Behavioral;