div_clk.vhd

来自「时钟分配和分路传输功能的VHDL语言程序」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY div_clk IS
  PORT(
    CLK, CLR: IN  STD_LOGIC;
    Q5 : OUT  STD_LOGIC);
END div_clk;

ARCHITECTURE a OF div_clk IS
  SIGNAL COUNTA: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
Q5<= COUNTA(1);
P1:PROCESS (CLK,CLR)
  BEGIN
  IF (CLR='1') THEN
    COUNTA<="000";
  ELSIF FALLING_EDGE(CLK) THEN
    IF(COUNTA<="011") THEN
      COUNTA<= COUNTA+1;
    ELSE 
      COUNTA<="000";
    END IF;
  END IF;
END PROCESS P1;
end a;