exchange_mod.vhd

时钟分配和分路传输功能的VHDL语言程序

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--
-- Title       : exchange_mod
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
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--
-- File        : exchange_mod.vhd
-- Generated   : Thu Nov 13 14:55:02 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {exchange_mod} architecture {a}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

entity exchange_mod is
port(  DATA_IN: in std_logic_vector( 7 downto 0);
    WE : in std_logic;
    CLR : in std_logic;
    dsp_clk: in std_logic;
    CS : in std_logic;
    EN_T_MODEL : out std_logic;
    EN_M_MODEL : out std_logic;
    EN_S_MODEL : out std_logic);
end exchange_mod;

architecture a of exchange_mod is
signal T_MODEL , S_MODEL, M_MODEL : std_logic;
signal DATA_TEMP : std_logic_vector(7 downto 0);

begin
EN_T_MODEL <= T_MODEL;
EN_S_MODEL <= S_MODEL;
EN_M_MODEL <= M_MODEL;
process(CLR,CS,WE,DATA_IN,dsp_clk)
begin
  if CLR ='1' then
    DATA_TEMP <= ( others=>'0');
  elsif rising_edge(dsp_clk) then
  if (CS ='0' and WE='0') then
      DATA_TEMP <= DATA_IN;
  else 
      data_temp <= data_temp;
  end if;
  end if;
end process;

process(DATA_TEMP,CLR,dsp_clk)
begin
  if CLR='1' then
    T_MODEL <='0';
    S_MODEL <='0';
    M_MODEL <='0';
  elsif rising_edge(dsp_clk) then
    case DATA_TEMP is
      when "00001010" =>
        S_MODEL <= '1';
        T_MODEL <= '0';
        M_MODEL <='0';
      when "10100000" =>
        S_MODEL <= '0';
        T_MODEL <= '1';
        M_MODEL <= '0';
      when "00000101" =>
        S_MODEL <= '0';
        T_MODEL <= '0';
        M_MODEL <= '1';
      when others =>
        T_MODEL <= T_MODEL;
        S_MODEL <= S_MODEL;
        M_MODEL  <= M_MODEL;
    end case;
  end if;
end process;
end a;