data_mem4.vhd

时钟分配和分路传输功能的VHDL语言程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity data_mem4 is
port(
din : in std_logic_vector(7 downto 0);
wr : in std_logic;
clk : in std_logic;
clr : in std_logic;
flg_out : out std_logic;
douta : out std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0);
doutc : out std_logic_vector(7 downto 0);
doutd : out std_logic_vector(7 downto 0)
);
end data_mem4;

architecture a of data_mem4 is

signal qa,qb,qc,qd : std_logic_vector(7 downto 0);
signal seg : std_logic_vector( 2 downto 0);
signal wr_tmp,t1,t2,out_en : std_logic;
begin

P1:process(CLK,CLR)
begin
  if CLR ='1' then
    T1<='0';
    T2<='0';
  elsif rising_edge(clk) THEN
    T1<=WR;
    if WR='1' and T1= '0'then
      T2<='1';
    else
      T2<='0';
    end if;
  END IF;
END PROCESS P1;
wr_tmp<=T2;
process(clk,clr,wr_tmp)
begin
if clr='1' then
  qa <= (others=>'0');
  qb <= (others=>'0');
  qc <= (others=>'0');
  qd <= (others=>'0');
  seg <= (others=> '0');
--  out_en <= '0';
elsif rising_edge(clk) then
  case seg is
    when "000" => 
--      out_en <='0';
      flg_out <='0';
      if wr_tmp='1' then
        qa<= din;
        seg<="001";
      else
        qa<= qa;
        seg <= seg;
      end if;
    when "001" =>
      if wr_tmp='1' then
        qb<= din;
        seg<="010";
      else
        qb<= qb;
        seg <= seg;
      end if;
    when "010" =>
      if wr_tmp='1' then
        qc<= din;
        seg<="011";
      else
        qc<= qc;
        seg <= seg;
      end if;
    when "011" =>
      if wr_tmp='1' then
        qd<= din;
        seg<="100";
      else
        qd<= qd;
        seg <= seg;
      end if;
    when "100" =>
      seg<="101";
      out_en <='1';
    when "101" =>
      seg<="110";
--      flg_out <= '1';
      out_en <='0';
    when "110" =>
      seg<="000";
      flg_out <= '1';
      out_en <='0';
    when others =>
      NULL;
  end case;
end if;
end process;
process(clk,clr,out_en)
begin
if clr='1' then
  douta<=(others=>'0');
  doutb<=(others=>'0');
  doutc<=(others=>'0');
  doutd<=(others=>'0');
elsif rising_edge(clk) then
    if out_en='1' then
    	douta<=qa;
	doutb<=qb;
	doutc<=qc;
	doutd<=qd;
    end if;
end if;
end process;
end a;