debouncing.vhd

时钟分配和分路传输功能的VHDL语言程序

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--
-- Title       : debouncing
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
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--
-- File        : debouncing.vhd
-- Generated   : Tue Nov  4 13:37:53 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {da_control} architecture {arch}}
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DEBOUNCING IS
 PORT(DIN ,CLK : IN STD_LOGIC;
      DOUT : OUT STD_LOGIC);
 END;
ARCHITECTURE A OF DEBOUNCING IS
  
 
component dffa
   port (CLK,RESET,DIN: in std_logic;
    		DOUT: out std_logic );
end component ;
 


SIGNAL VCC,D1,D0,Q0,Q1 : STD_LOGIC;
BEGIN
  VCC <= '1';
--  INV_D <= NOT DIN;
  DFF1 : DFFa PORT MAP (DIN => VCC,DOUT => Q0,CLK => CLK,RESET => DIN);
  DFF2 : DFFa PORT MAP (DIN => VCC,DOUT => Q1,CLK => CLK,RESET => Q0);
 PROCESS(CLK)
  BEGIN
     IF CLK ' EVENT AND CLK = '1' THEN
        D0 <= NOT Q1;
        D1 <= D0;
  	END IF;
 END PROCESS;
DOUT <=D1 AND NOT D0;
END A;