debounce.vhd

时钟分配和分路传输功能的VHDL语言程序

--------------------------------------------------------------------------------------------------
--
-- Title       : Debounce
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
---------------------------------------------------------------------------------------------------
--
-- File        : Debounce.vhd
-- Generated   : Tue Nov 21 10:28:46 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description : 
--
---------------------------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {lcd_port} architecture {a}}
--*************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--**************************************************************
ENTITY Debounce is
  PORT(
     clr : in std_logic;
     CLK  : IN    STD_LOGIC;        -- CLOCK
     DIN  : IN    STD_LOGIC;        -- Input Signal
     DOUT   : OUT   STD_LOGIC         -- Debounce O/P
    );
END Debounce;

--**************************************************************
ARCHITECTURE a OF Debounce IS
  SIGNAL SAMPLE, DLY, NDLY: STD_LOGIC;  -- Binary 
BEGIN

Free_Counter : Block    -- 计数器  & 产生扫描信号               
   Signal   Q_debou  : STD_LOGIC_VECTOR(9 DOWNTO 0);
  Signal  d_debou : STD_LOGIC;
Begin
  
  PROCESS (CLK,CLR)          -- 计数器计数       
  Begin
    if clr ='1' then
      Q_debou <= (others=> '0');
      d_debou <='0';
    elsif CLK 'Event AND CLK='1' then
      if Q_debou ="1111111111" then
        Q_debou <= (others => '0');
      else
        Q_debou <= Q_debou +1;
      end if;
      d_debou <= Q_debou(9);              
      SAMPLE <= Q_debou(9) AND (NOT d_debou);    --产生125HZ脉冲?    
    END IF;
  END PROCESS;
  
  --SAMPLE <= Q(1) AND NOT d_debou;  
END Block Free_Counter;                      


Debunce : Block              -- Debounce
  SIGNAL Dc, Dd, S, R : STD_LOGIC;  
Begin
  Process (CLK)
  Begin
    IF CLK 'EVENT AND CLK='1' THEN
      IF SAMPLE = '1' THEN
        Dd <= Dc; Dc <= DIN;    -- Two Stage Delay
        S <= Dc AND Dd;        -- Generate S、R  
        R <= (NOT Dc) AND (NOT Dd);
      END IF;    
    DLY <= R NOR NDLY;      -- Debounce O/P
  NDLY <=S NOR DLY;  
  DOUT <= DLY;
  END IF;
  End Process;  

End Block Debunce;
END a;