clock.fit.rpt

用Verilog HDL 实现时钟(时和分)

; Name                                                                           ; Value            ;
+--------------------------------------------------------------------------------+------------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff               ;
; Mid Wire Use - Fit Attempt 1                                                   ; 22               ;
; Mid Slack - Fit Attempt 1                                                      ; -21961           ;
; Internal Atom Count - Fit Attempt 1                                            ; 99               ;
; LE/ALM Count - Fit Attempt 1                                                   ; 99               ;
; LAB Count - Fit Attempt 1                                                      ; 19               ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.263            ;
; Inputs per LAB - Fit Attempt 1                                                 ; 5.053            ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.947            ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:19             ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:16;1:3         ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:16;1:3         ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:16;1:3         ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:16;1:3         ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:16;1:3         ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:19             ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:16;1:3         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:16;1:3         ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:2;1:14;2:2;3:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:3;1:12;2:4     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:19             ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:3;1:16         ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:17;1:2         ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:7;1:12         ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:16;1:3         ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:19             ;
; LEs in Chains - Fit Attempt 1                                                  ; 23               ;
; LEs in Long Chains - Fit Attempt 1                                             ; 23               ;
; LABs with Chains - Fit Attempt 1                                               ; 3                ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0                ;
; Time - Fit Attempt 1                                                           ; 0                ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.015            ;
+--------------------------------------------------------------------------------+------------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 5      ;
; Early Slack - Fit Attempt 1         ; -29737 ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 10     ;
; Mid Slack - Fit Attempt 1           ; -26759 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Late Wire Use - Fit Attempt 1       ; 11     ;
; Late Slack - Fit Attempt 1          ; -26759 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -24730 ;
; Early Wire Use - Fit Attempt 1      ; 8      ;
; Peak Regional Wire - Fit Attempt 1  ; 8      ;
; Mid Slack - Fit Attempt 1           ; -25914 ;
; Late Slack - Fit Attempt 1          ; -25914 ;
; Late Wire Use - Fit Attempt 1       ; 10     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.094  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Jan 20 14:10:07 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clock -c clock
Info: Selected device EPM240T100C5 for design "clock"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "second" to use Global clock
    Info: Destination "second" may be non-global or may not use global clock
Info: Automatically promoted signal "cn" to use Global clock
Info: Automatically promoted signal "Mux11~29" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 4.644 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y4; Fanout = 1; REG Node = 'segdat_reg[0]'
    Info: 2: + IC(2.322 ns) + CELL(2.322 ns) = 4.644 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'segdat[0]'
    Info: Total cell delay = 2.322 ns ( 50.00 % )
    Info: Total interconnect delay = 2.322 ns ( 50.00 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 7% of the available device resources
    Info: Peak interconnect usage is 7% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin segdat[7] has GND driving its datain port
    Info: Pin sl[4] has VCC driving its datain port
    Info: Pin sl[5] has VCC driving its datain port
    Info: Pin fm has VCC driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 165 megabytes of memory during processing
    Info: Processing ended: Tue Jan 20 14:10:12 2009
    Info: Elapsed time: 00:00:05


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.fit.smsg.