📄 prev_cmp_beep.qmsg
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{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "beep 0 " "Info: Pin \"beep\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/FPGA/verilongsample/beep/beep.fit.smsg " "Info: Generated suppressed messages file D:/FPGA/verilongsample/beep/beep.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "180 " "Info: Allocated 180 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 06 11:53:45 2009 " "Info: Processing ended: Tue Jan 06 11:53:45 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 06 11:53:49 2009 " "Info: Processing started: Tue Jan 06 11:53:49 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off beep -c beep " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off beep -c beep" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 06 11:53:59 2009 " "Info: Processing ended: Tue Jan 06 11:53:59 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 06 11:54:01 2009 " "Info: Processing started: Tue Jan 06 11:54:01 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off beep -c beep --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off beep -c beep --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register buzzer:inst\|clk_div2\[8\] register buzzer:inst\|out 150.51 MHz 6.644 ns Internal " "Info: Clock \"clk\" has Internal fmax of 150.51 MHz between source register \"buzzer:inst\|clk_div2\[8\]\" and destination register \"buzzer:inst\|out\" (period= 6.644 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.373 ns + Longest register register " "Info: + Longest register to register delay is 6.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buzzer:inst\|clk_div2\[8\] 1 REG LCFF_X38_Y20_N17 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y20_N17; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[8\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.123 ns) + CELL(0.366 ns) 1.489 ns buzzer:inst\|Equal5~93 2 COMB LCCOMB_X36_Y20_N8 2 " "Info: 2: + IC(1.123 ns) + CELL(0.366 ns) = 1.489 ns; Loc. = LCCOMB_X36_Y20_N8; Fanout = 2; COMB Node = 'buzzer:inst\|Equal5~93'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { buzzer:inst|clk_div2[8] buzzer:inst|Equal5~93 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 76 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.377 ns) + CELL(0.589 ns) 2.455 ns buzzer:inst\|Equal7~92 3 COMB LCCOMB_X36_Y20_N22 2 " "Info: 3: + IC(0.377 ns) + CELL(0.589 ns) = 2.455 ns; Loc. = LCCOMB_X36_Y20_N22; Fanout = 2; COMB Node = 'buzzer:inst\|Equal7~92'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.966 ns" { buzzer:inst|Equal5~93 buzzer:inst|Equal7~92 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.206 ns) 3.035 ns buzzer:inst\|Equal7~94 4 COMB LCCOMB_X36_Y20_N14 2 " "Info: 4: + IC(0.374 ns) + CELL(0.206 ns) = 3.035 ns; Loc. = LCCOMB_X36_Y20_N14; Fanout = 2; COMB Node = 'buzzer:inst\|Equal7~94'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.580 ns" { buzzer:inst|Equal7~92 buzzer:inst|Equal7~94 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.608 ns) + CELL(0.366 ns) 4.009 ns buzzer:inst\|Selector21~527 5 COMB LCCOMB_X35_Y20_N8 1 " "Info: 5: + IC(0.608 ns) + CELL(0.366 ns) = 4.009 ns; Loc. = LCCOMB_X35_Y20_N8; Fanout = 1; COMB Node = 'buzzer:inst\|Selector21~527'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.974 ns" { buzzer:inst|Equal7~94 buzzer:inst|Selector21~527 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.053 ns) + CELL(0.624 ns) 5.686 ns buzzer:inst\|Selector21~534 6 COMB LCCOMB_X39_Y20_N2 1 " "Info: 6: + IC(1.053 ns) + CELL(0.624 ns) = 5.686 ns; Loc. = LCCOMB_X39_Y20_N2; Fanout = 1; COMB Node = 'buzzer:inst\|Selector21~534'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.677 ns" { buzzer:inst|Selector21~527 buzzer:inst|Selector21~534 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 49 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.206 ns) 6.265 ns buzzer:inst\|out~703 7 COMB LCCOMB_X39_Y20_N4 1 " "Info: 7: + IC(0.373 ns) + CELL(0.206 ns) = 6.265 ns; Loc. = LCCOMB_X39_Y20_N4; Fanout = 1; COMB Node = 'buzzer:inst\|out~703'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.579 ns" { buzzer:inst|Selector21~534 buzzer:inst|out~703 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.373 ns buzzer:inst\|out 8 REG LCFF_X39_Y20_N5 10 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 6.373 ns; Loc. = LCFF_X39_Y20_N5; Fanout = 10; REG Node = 'buzzer:inst\|out'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { buzzer:inst|out~703 buzzer:inst|out } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.465 ns ( 38.68 % ) " "Info: Total cell delay = 2.465 ns ( 38.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.908 ns ( 61.32 % ) " "Info: Total interconnect delay = 3.908 ns ( 61.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.373 ns" { buzzer:inst|clk_div2[8] buzzer:inst|Equal5~93 buzzer:inst|Equal7~92 buzzer:inst|Equal7~94 buzzer:inst|Selector21~527 buzzer:inst|Selector21~534 buzzer:inst|out~703 buzzer:inst|out } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.373 ns" { buzzer:inst|clk_div2[8] {} buzzer:inst|Equal5~93 {} buzzer:inst|Equal7~92 {} buzzer:inst|Equal7~94 {} buzzer:inst|Selector21~527 {} buzzer:inst|Selector21~534 {} buzzer:inst|out~703 {} buzzer:inst|out {} } { 0.000ns 1.123ns 0.377ns 0.374ns 0.608ns 1.053ns 0.373ns 0.000ns } { 0.000ns 0.366ns 0.589ns 0.206ns 0.366ns 0.624ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.007 ns - Smallest " "Info: - Smallest clock skew is -0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.125 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.160 ns) 1.160 ns clk 1 CLK PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.160 ns) = 1.160 ns; Loc. = PIN_91; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.000 ns) 1.411 ns clk~clkctrl 2 COMB CLKCTRL_G15 48 " "Info: 2: + IC(0.251 ns) + CELL(0.000 ns) = 1.411 ns; Loc. = CLKCTRL_G15; Fanout = 48; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.251 ns" { clk clk~clkctrl } "NODE_NAME" } } { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.048 ns) + CELL(0.666 ns) 3.125 ns buzzer:inst\|out 3 REG LCFF_X39_Y20_N5 10 " "Info: 3: + IC(1.048 ns) + CELL(0.666 ns) = 3.125 ns; Loc. = LCFF_X39_Y20_N5; Fanout = 10; REG Node = 'buzzer:inst\|out'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.714 ns" { clk~clkctrl buzzer:inst|out } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.826 ns ( 58.43 % ) " "Info: Total cell delay = 1.826 ns ( 58.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.299 ns ( 41.57 % ) " "Info: Total interconnect delay = 1.299 ns ( 41.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.125 ns" { clk clk~clkctrl buzzer:inst|out } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.125 ns" { clk {} clk~combout {} clk~clkctrl {} buzzer:inst|out {} } { 0.000ns 0.000ns 0.251ns 1.048ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.132 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.160 ns) 1.160 ns clk 1 CLK PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.160 ns) = 1.160 ns; Loc. = PIN_91; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.000 ns) 1.411 ns clk~clkctrl 2 COMB CLKCTRL_G15 48 " "Info: 2: + IC(0.251 ns) + CELL(0.000 ns) = 1.411 ns; Loc. = CLKCTRL_G15; Fanout = 48; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.251 ns" { clk clk~clkctrl } "NODE_NAME" } } { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.055 ns) + CELL(0.666 ns) 3.132 ns buzzer:inst\|clk_div2\[8\] 3 REG LCFF_X38_Y20_N17 8 " "Info: 3: + IC(1.055 ns) + CELL(0.666 ns) = 3.132 ns; Loc. = LCFF_X38_Y20_N17; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[8\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.721 ns" { clk~clkctrl buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.826 ns ( 58.30 % ) " "Info: Total cell delay = 1.826 ns ( 58.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.306 ns ( 41.70 % ) " "Info: Total interconnect delay = 1.306 ns ( 41.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.132 ns" { clk clk~clkctrl buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.132 ns" { clk {} clk~combout {} clk~clkctrl {} buzzer:inst|clk_div2[8] {} } { 0.000ns 0.000ns 0.251ns 1.055ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.125 ns" { clk clk~clkctrl buzzer:inst|out } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.125 ns" { clk {} clk~combout {} clk~clkctrl {} buzzer:inst|out {} } { 0.000ns 0.000ns 0.251ns 1.048ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.132 ns" { clk clk~clkctrl buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.132 ns" { clk {} clk~combout {} clk~clkctrl {} buzzer:inst|clk_div2[8] {} } { 0.000ns 0.000ns 0.251ns 1.055ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.373 ns" { buzzer:inst|clk_div2[8] buzzer:inst|Equal5~93 buzzer:inst|Equal7~92 buzzer:inst|Equal7~94 buzzer:inst|Selector21~527 buzzer:inst|Selector21~534 buzzer:inst|out~703 buzzer:inst|out } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.373 ns" { buzzer:inst|clk_div2[8] {} buzzer:inst|Equal5~93 {} buzzer:inst|Equal7~92 {} buzzer:inst|Equal7~94 {} buzzer:inst|Selector21~527 {} buzzer:inst|Selector21~534 {} buzzer:inst|out~703 {} buzzer:inst|out {} } { 0.000ns 1.123ns 0.377ns 0.374ns 0.608ns 1.053ns 0.373ns 0.000ns } { 0.000ns 0.366ns 0.589ns 0.206ns 0.366ns 0.624ns 0.206ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.125 ns" { clk clk~clkctrl buzzer:inst|out } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.125 ns" { clk {} clk~combout {} clk~clkctrl {} buzzer:inst|out {} } { 0.000ns 0.000ns 0.251ns 1.048ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.132 ns" { clk clk~clkctrl buzzer:inst|clk_div2[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.132 ns" { clk {} clk~combout {} clk~clkctrl {} buzzer:inst|clk_div2[8] {} } { 0.000ns 0.000ns 0.251ns 1.055ns } { 0.000ns 1.160ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "buzzer:inst\|clk_div2\[11\] reset clk 5.921 ns register " "Info: tsu for register \"buzzer:inst\|clk_div2\[11\]\" (data pin = \"reset\", clock pin = \"clk\") is 5.921 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.093 ns + Longest pin register " "Info: + Longest pin to register delay is 9.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.170 ns) 1.170 ns reset 1 PIN PIN_92 37 " "Info: 1: + IC(0.000 ns) + CELL(1.170 ns) = 1.170 ns; Loc. = PIN_92; Fanout = 37; PIN Node = 'reset'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 176 72 240 192 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.319 ns) + CELL(0.606 ns) 5.095 ns buzzer:inst\|clk_div2\[6\]~2042 2 COMB LCCOMB_X35_Y20_N16 3 " "Info: 2: + IC(3.319 ns) + CELL(0.606 ns) = 5.095 ns; Loc. = LCCOMB_X35_Y20_N16; Fanout = 3; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2042'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.925 ns" { reset buzzer:inst|clk_div2[6]~2042 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.370 ns) 5.843 ns buzzer:inst\|clk_div2\[6\]~2043 3 COMB LCCOMB_X35_Y20_N24 1 " "Info: 3: + IC(0.378 ns) + CELL(0.370 ns) = 5.843 ns; Loc. = LCCOMB_X35_Y20_N24; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2043'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.748 ns" { buzzer:inst|clk_div2[6]~2042 buzzer:inst|clk_div2[6]~2043 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.650 ns) 7.540 ns buzzer:inst\|clk_div2\[6\]~2048 4 COMB LCCOMB_X38_Y20_N30 1 " "Info: 4: + IC(1.047 ns) + CELL(0.650 ns) = 7.540 ns; Loc. = LCCOMB_X38_Y20_N30; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2048'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.697 ns" { buzzer:inst|clk_div2[6]~2043 buzzer:inst|clk_div2[6]~2048 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.202 ns) 8.106 ns buzzer:inst\|clk_div2\[6\]~2053 5 COMB LCCOMB_X38_Y20_N26 13 " "Info: 5: + IC(0.364 ns) + CELL(0.202 ns) = 8.106 ns; Loc. = LCCOMB_X38_Y20_N26; Fanout = 13; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2053'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.566 ns" { buzzer:inst|clk_div2[6]~2048 buzzer:inst|clk_div2[6]~2053 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.327 ns) + CELL(0.660 ns) 9.093 ns buzzer:inst\|clk_div2\[11\] 6 REG LCFF_X38_Y20_N23 8 " "Info: 6: + IC(0.327 ns) + CELL(0.660 ns) = 9.093 ns; Loc. = LCFF_X38_Y20_N23; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[11\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.987 ns" { buzzer:inst|clk_div2[6]~2053 buzzer:inst|clk_div2[11] } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.658 ns ( 40.23 % ) " "Info: Total cell delay = 3.658 ns ( 40.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.435 ns ( 59.77 % ) " "Info: Total interconnect delay = 5.435 ns ( 59.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.093 ns" { reset buzzer:inst|clk_div2[6]~2042 buzzer:inst|clk_div2[6]~2043 buzzer:inst|clk_div2[6]~2048 buzzer:inst|clk_div2[6]~2053 buzzer:inst|clk_div2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.093 ns" { reset {} reset~combout {} buzzer:inst|clk_div2[6]~2042 {} buzzer:inst|clk_div2[6]~2043 {} buzzer:inst|clk_div2[6]~2048 {} buzzer:inst|clk_div2[6]~2053 {} buzzer:inst|clk_div2[11] {} } { 0.000ns 0.000ns 3.319ns 0.378ns 1.047ns 0.364ns 0.327ns } { 0.000ns 1.170ns 0.606ns 0.370ns 0.650ns 0.202ns 0.660ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.132 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.160 ns) 1.160 ns clk 1 CLK PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.160 ns) = 1.160 ns; Loc. = PIN_91; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.000 ns) 1.411 ns clk~clkctrl 2 COMB CLKCTRL_G15 48 " "Info: 2: + IC(0.251 ns) + CELL(0.000 ns) = 1.411 ns; Loc. = CLKCTRL_G15; Fanout = 48; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.251 ns" { clk clk~clkctrl } "NODE_NAME" } } { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.055 ns) + CELL(0.666 ns) 3.132 ns buzzer:inst\|cl⌨️ 快捷键说明
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