beep.fit.summary

来自「verilog写的控制喇叭的FPGA程序。」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Tue Jan 06 11:53:45 2009
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
Revision Name : beep
Top-level Entity Name : beep
Family : Cyclone II
Device : EP2C20Q240C8
Timing Models : Final
Total logic elements : 110 / 18,752 ( < 1 % )
    Total combinational functions : 110 / 18,752 ( < 1 % )
    Dedicated logic registers : 48 / 18,752 ( < 1 % )
Total registers : 48
Total pins : 3 / 142 ( 2 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )