prev_cmp_beep.qmsg

verilog写的控制喇叭的FPGA程序。

{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|beep\|buzzer:inst\|state " "Info: Encoding result for state machine \"\|beep\|buzzer:inst\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "8 " "Info: Completed encoding using 8 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.111 " "Info: Encoded state bit \"buzzer:inst\|state.111\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.110 " "Info: Encoded state bit \"buzzer:inst\|state.110\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.101 " "Info: Encoded state bit \"buzzer:inst\|state.101\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.100 " "Info: Encoded state bit \"buzzer:inst\|state.100\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.011 " "Info: Encoded state bit \"buzzer:inst\|state.011\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.010 " "Info: Encoded state bit \"buzzer:inst\|state.010\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.001 " "Info: Encoded state bit \"buzzer:inst\|state.001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.000 " "Info: Encoded state bit \"buzzer:inst\|state.000\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.000 00000000 " "Info: State \"\|beep\|buzzer:inst\|state.000\" uses code string \"00000000\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.001 00000011 " "Info: State \"\|beep\|buzzer:inst\|state.001\" uses code string \"00000011\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.010 00000101 " "Info: State \"\|beep\|buzzer:inst\|state.010\" uses code string \"00000101\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.011 00001001 " "Info: State \"\|beep\|buzzer:inst\|state.011\" uses code string \"00001001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.100 00010001 " "Info: State \"\|beep\|buzzer:inst\|state.100\" uses code string \"00010001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.101 00100001 " "Info: State \"\|beep\|buzzer:inst\|state.101\" uses code string \"00100001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.110 01000001 " "Info: State \"\|beep\|buzzer:inst\|state.110\" uses code string \"01000001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.111 10000001 " "Info: State \"\|beep\|buzzer:inst\|state.111\" uses code string \"10000001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 3 " "Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "buzzer:inst\|state~71 " "Info: Register \"buzzer:inst\|state~71\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "buzzer:inst\|state~72 " "Info: Register \"buzzer:inst\|state~72\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "buzzer:inst\|state~73 " "Info: Register \"buzzer:inst\|state~73\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "113 " "Info: Implemented 113 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "110 " "Info: Implemented 110 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 06 11:53:31 2009 " "Info: Processing ended: Tue Jan 06 11:53:31 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 06 11:53:33 2009 " "Info: Processing started: Tue Jan 06 11:53:33 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off beep -c beep " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off beep -c beep" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "beep EP2C20Q240C8 " "Info: Selected device EP2C20Q240C8 for design \"beep\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" {  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 4 " "Info: Pin ~ASDO~ is reserved at location 4" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 5 " "Info: Pin ~nCSO~ is reserved at location 5" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ 127 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location 127" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 91 (CLK15, LVDSCLK7p, Input)) " "Info: Automatically promoted node clk (placed in PIN 91 (CLK15, LVDSCLK7p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G15 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { clk } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}