prev_cmp_beep.qmsg

verilog写的控制喇叭的FPGA程序。

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(55) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(55): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 55 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(62) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(62): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(66) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(66): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(73) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(73): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(77) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(77): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(84) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(84): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(88) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(88): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 88 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(95) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(95): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 95 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(99) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(99): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 99 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(106) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(106): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(110) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(110): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(117) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(117): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 117 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(121) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(121): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 121 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(128) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(128): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 128 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(132) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(132): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 132 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|beep\|buzzer:inst\|state 8 " "Info: State machine \"\|beep\|buzzer:inst\|state\" contains 8 states" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|beep\|buzzer:inst\|state " "Info: Selected Auto state machine encoding method for state machine \"\|beep\|buzzer:inst\|state\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}