beep.map.qmsg

verilog写的控制喇叭的FPGA程序。

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(73) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(73): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(77) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(77): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(84) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(84): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(88) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(88): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 88 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(95) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(95): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 95 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(99) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(99): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 99 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(106) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(106): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(110) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(110): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(117) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(117): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 117 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(121) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(121): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 121 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(128) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(128): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 128 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(132) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(132): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 132 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|beep\|buzzer:inst\|state 8 " "Info: State machine \"\|beep\|buzzer:inst\|state\" contains 8 states" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|beep\|buzzer:inst\|state " "Info: Selected Auto state machine encoding method for state machine \"\|beep\|buzzer:inst\|state\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|beep\|buzzer:inst\|state " "Info: Encoding result for state machine \"\|beep\|buzzer:inst\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "8 " "Info: Completed encoding using 8 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.111 " "Info: Encoded state bit \"buzzer:inst\|state.111\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.110 " "Info: Encoded state bit \"buzzer:inst\|state.110\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.101 " "Info: Encoded state bit \"buzzer:inst\|state.101\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.100 " "Info: Encoded state bit \"buzzer:inst\|state.100\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.011 " "Info: Encoded state bit \"buzzer:inst\|state.011\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.010 " "Info: Encoded state bit \"buzzer:inst\|state.010\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.001 " "Info: Encoded state bit \"buzzer:inst\|state.001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "buzzer:inst\|state.000 " "Info: Encoded state bit \"buzzer:inst\|state.000\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.000 00000000 " "Info: State \"\|beep\|buzzer:inst\|state.000\" uses code string \"00000000\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.001 00000011 " "Info: State \"\|beep\|buzzer:inst\|state.001\" uses code string \"00000011\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.010 00000101 " "Info: State \"\|beep\|buzzer:inst\|state.010\" uses code string \"00000101\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.011 00001001 " "Info: State \"\|beep\|buzzer:inst\|state.011\" uses code string \"00001001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.100 00010001 " "Info: State \"\|beep\|buzzer:inst\|state.100\" uses code string \"00010001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.101 00100001 " "Info: State \"\|beep\|buzzer:inst\|state.101\" uses code string \"00100001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.110 01000001 " "Info: State \"\|beep\|buzzer:inst\|state.110\" uses code string \"01000001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|beep\|buzzer:inst\|state.111 10000001 " "Info: State \"\|beep\|buzzer:inst\|state.111\" uses code string \"10000001\"" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 3 " "Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "buzzer:inst\|state~71 " "Info: Register \"buzzer:inst\|state~71\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "buzzer:inst\|state~72 " "Info: Register \"buzzer:inst\|state~72\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "buzzer:inst\|state~73 " "Info: Register \"buzzer:inst\|state~73\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "113 " "Info: Implemented 113 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "110 " "Info: Implemented 110 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 06 11:55:05 2009 " "Info: Processing ended: Tue Jan 06 11:55:05 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}