beep.fit.qmsg

verilog写的控制喇叭的FPGA程序。

{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.219 ns register register " "Info: Estimated most critical path is register to register delay of 7.219 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buzzer:inst\|clk_div2\[3\] 1 REG LAB_X38_Y20 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X38_Y20; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { buzzer:inst|clk_div2[3] } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.370 ns) 1.574 ns buzzer:inst\|Equal6~110 2 COMB LAB_X36_Y20 1 " "Info: 2: + IC(1.204 ns) + CELL(0.370 ns) = 1.574 ns; Loc. = LAB_X36_Y20; Fanout = 1; COMB Node = 'buzzer:inst\|Equal6~110'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { buzzer:inst|clk_div2[3] buzzer:inst|Equal6~110 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 2.385 ns buzzer:inst\|Equal6~111 3 COMB LAB_X36_Y20 2 " "Info: 3: + IC(0.605 ns) + CELL(0.206 ns) = 2.385 ns; Loc. = LAB_X36_Y20; Fanout = 2; COMB Node = 'buzzer:inst\|Equal6~111'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { buzzer:inst|Equal6~110 buzzer:inst|Equal6~111 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 3.196 ns buzzer:inst\|clk_div2\[6\]~2045 4 COMB LAB_X36_Y20 1 " "Info: 4: + IC(0.441 ns) + CELL(0.370 ns) = 3.196 ns; Loc. = LAB_X36_Y20; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2045'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { buzzer:inst|Equal6~111 buzzer:inst|clk_div2[6]~2045 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.125 ns) + CELL(0.370 ns) 4.691 ns buzzer:inst\|clk_div2\[6\]~2047 5 COMB LAB_X38_Y20 1 " "Info: 5: + IC(1.125 ns) + CELL(0.370 ns) = 4.691 ns; Loc. = LAB_X38_Y20; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2047'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { buzzer:inst|clk_div2[6]~2045 buzzer:inst|clk_div2[6]~2047 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 5.502 ns buzzer:inst\|clk_div2\[6\]~2048 6 COMB LAB_X38_Y20 1 " "Info: 6: + IC(0.605 ns) + CELL(0.206 ns) = 5.502 ns; Loc. = LAB_X38_Y20; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2048'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { buzzer:inst|clk_div2[6]~2047 buzzer:inst|clk_div2[6]~2048 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.534 ns) 6.196 ns buzzer:inst\|clk_div2\[6\]~2053 7 COMB LAB_X38_Y20 13 " "Info: 7: + IC(0.160 ns) + CELL(0.534 ns) = 6.196 ns; Loc. = LAB_X38_Y20; Fanout = 13; COMB Node = 'buzzer:inst\|clk_div2\[6\]~2053'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.694 ns" { buzzer:inst|clk_div2[6]~2048 buzzer:inst|clk_div2[6]~2053 } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.660 ns) 7.219 ns buzzer:inst\|clk_div2\[10\] 8 REG LAB_X38_Y20 8 " "Info: 8: + IC(0.363 ns) + CELL(0.660 ns) = 7.219 ns; Loc. = LAB_X38_Y20; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[10\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.023 ns" { buzzer:inst|clk_div2[6]~2053 buzzer:inst|clk_div2[10] } "NODE_NAME" } } { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.716 ns ( 37.62 % ) " "Info: Total cell delay = 2.716 ns ( 37.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.503 ns ( 62.38 % ) " "Info: Total interconnect delay = 4.503 ns ( 62.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.219 ns" { buzzer:inst|clk_div2[3] buzzer:inst|Equal6~110 buzzer:inst|Equal6~111 buzzer:inst|clk_div2[6]~2045 buzzer:inst|clk_div2[6]~2047 buzzer:inst|clk_div2[6]~2048 buzzer:inst|clk_div2[6]~2053 buzzer:inst|clk_div2[10] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X25_Y14 X37_Y27 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "beep 0 " "Info: Pin \"beep\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/FPGA/verilongsample/beep/beep.fit.smsg " "Info: Generated suppressed messages file D:/FPGA/verilongsample/beep/beep.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "180 " "Info: Allocated 180 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 06 11:53:45 2009 " "Info: Processing ended: Tue Jan 06 11:53:45 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}