beep.map.rpt

verilog写的控制喇叭的FPGA程序。

; Total fan-out                               ; 493   ;
; Average fan-out                             ; 3.06  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |beep                      ; 110 (0)           ; 48 (0)       ; 0           ; 0            ; 0       ; 0         ; 3    ; 0            ; |beep               ;              ;
;    |buzzer:inst|           ; 110 (110)         ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |beep|buzzer:inst   ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------+
; State Machine - |beep|buzzer:inst|state                                                                   ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
; Name      ; state.111 ; state.110 ; state.101 ; state.100 ; state.011 ; state.010 ; state.001 ; state.000 ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
; state.000 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ;
; state.001 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 1         ;
; state.010 ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 1         ;
; state.011 ; 0         ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 1         ;
; state.100 ; 0         ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 1         ;
; state.101 ; 0         ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 1         ;
; state.110 ; 0         ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ;
; state.111 ; 1         ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ; 1         ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; buzzer:inst|state~71                  ; Lost fanout        ;
; buzzer:inst|state~72                  ; Lost fanout        ;
; buzzer:inst|state~73                  ; Lost fanout        ;
; Total Number of Removed Registers = 3 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 48    ;
; Number of registers using Synchronous Clear  ; 43    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 13    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |beep|buzzer:inst|clk_div1[1] ;
; 18:1               ; 13 bits   ; 156 LEs       ; 13 LEs               ; 143 LEs                ; Yes        ; |beep|buzzer:inst|clk_div2[6] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+


+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: buzzer:inst ;
+----------------+-------+---------------------------------+
; Parameter Name ; Value ; Type                            ;
+----------------+-------+---------------------------------+
; duo            ; 3822  ; Signed Integer                  ;
; lai            ; 3405  ; Signed Integer                  ;
; mi             ; 3034  ; Signed Integer                  ;
; fa             ; 2865  ; Signed Integer                  ;
; suo            ; 2551  ; Signed Integer                  ;
; la             ; 2273  ; Signed Integer                  ;
; xi             ; 2024  ; Signed Integer                  ;
; duo1           ; 1911  ; Signed Integer                  ;
+----------------+-------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Tue Jan 06 11:55:01 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off beep -c beep
Info: Found 1 design units, including 1 entities, in source file beep.bdf
    Info: Found entity 1: beep
Warning (10229): Verilog HDL Expression warning at buzzer.v(52): truncated literal to match 22 bits
Warning (10229): Verilog HDL Expression warning at buzzer.v(63): truncated literal to match 22 bits
Warning (10229): Verilog HDL Expression warning at buzzer.v(74): truncated literal to match 22 bits
Warning (10229): Verilog HDL Expression warning at buzzer.v(85): truncated literal to match 22 bits
Warning (10229): Verilog HDL Expression warning at buzzer.v(96): truncated literal to match 22 bits
Warning (10229): Verilog HDL Expression warning at buzzer.v(107): truncated literal to match 22 bits
Warning (10229): Verilog HDL Expression warning at buzzer.v(118): truncated literal to match 22 bits
Warning (10229): Verilog HDL Expression warning at buzzer.v(129): truncated literal to match 22 bits
Info: Found 1 design units, including 1 entities, in source file buzzer.v
    Info: Found entity 1: buzzer
Info: Elaborating entity "beep" for the top level hierarchy
Warning: Processing legacy GDF or BDF entity "beep" with Max+Plus II bus and instance naming rules
Info: Elaborating entity "buzzer" for hierarchy "buzzer:inst"
Warning (10230): Verilog HDL assignment warning at buzzer.v(51): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at buzzer.v(55): truncated value with size 32 to match size of target (13)
Warning (10230): Verilog HDL assignment warning at buzzer.v(62): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at buzzer.v(66): truncated value with size 32 to match size of target (13)
Warning (10230): Verilog HDL assignment warning at buzzer.v(73): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at buzzer.v(77): truncated value with size 32 to match size of target (13)
Warning (10230): Verilog HDL assignment warning at buzzer.v(84): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at buzzer.v(88): truncated value with size 32 to match size of target (13)
Warning (10230): Verilog HDL assignment warning at buzzer.v(95): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at buzzer.v(99): truncated value with size 32 to match size of target (13)
Warning (10230): Verilog HDL assignment warning at buzzer.v(106): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at buzzer.v(110): truncated value with size 32 to match size of target (13)
Warning (10230): Verilog HDL assignment warning at buzzer.v(117): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at buzzer.v(121): truncated value with size 32 to match size of target (13)
Warning (10230): Verilog HDL assignment warning at buzzer.v(128): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at buzzer.v(132): truncated value with size 32 to match size of target (13)
Info: State machine "|beep|buzzer:inst|state" contains 8 states
Info: Selected Auto state machine encoding method for state machine "|beep|buzzer:inst|state"
Info: Encoding result for state machine "|beep|buzzer:inst|state"
    Info: Completed encoding using 8 state bits
        Info: Encoded state bit "buzzer:inst|state.111"
        Info: Encoded state bit "buzzer:inst|state.110"
        Info: Encoded state bit "buzzer:inst|state.101"
        Info: Encoded state bit "buzzer:inst|state.100"
        Info: Encoded state bit "buzzer:inst|state.011"
        Info: Encoded state bit "buzzer:inst|state.010"
        Info: Encoded state bit "buzzer:inst|state.001"
        Info: Encoded state bit "buzzer:inst|state.000"
    Info: State "|beep|buzzer:inst|state.000" uses code string "00000000"
    Info: State "|beep|buzzer:inst|state.001" uses code string "00000011"
    Info: State "|beep|buzzer:inst|state.010" uses code string "00000101"
    Info: State "|beep|buzzer:inst|state.011" uses code string "00001001"
    Info: State "|beep|buzzer:inst|state.100" uses code string "00010001"
    Info: State "|beep|buzzer:inst|state.101" uses code string "00100001"
    Info: State "|beep|buzzer:inst|state.110" uses code string "01000001"
    Info: State "|beep|buzzer:inst|state.111" uses code string "10000001"
Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below.
    Info: Register "buzzer:inst|state~71" lost all its fanouts during netlist optimizations.
    Info: Register "buzzer:inst|state~72" lost all its fanouts during netlist optimizations.
    Info: Register "buzzer:inst|state~73" lost all its fanouts during netlist optimizations.
Info: Implemented 113 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 110 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Allocated 143 megabytes of memory during processing
    Info: Processing ended: Tue Jan 06 11:55:05 2009
    Info: Elapsed time: 00:00:04