atmega16.tan.qmsg

基于FPGA的DDS正弦信号发生器,信号失真小

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 80 -32 136 96 "clk" "" } } } } { "d:/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "dds:inst\|cp_1k " "Info: Detected ripple clock \"dds:inst\|cp_1k\" as buffer" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 82 -1 0 } } { "d:/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "dds:inst\|cp_1k" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "dds:inst\|cp_65k " "Info: Detected ripple clock \"dds:inst\|cp_65k\" as buffer" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 80 -1 0 } } { "d:/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "dds:inst\|cp_65k" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "tx3:inst1\|clock " "Info: Detected ripple clock \"tx3:inst1\|clock\" as buffer" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 18 -1 0 } } { "d:/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx3:inst1\|clock" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dds:inst\|dds_m\[5\] register dds:inst\|dds_add\[9\] 96.21 MHz 10.394 ns Internal " "Info: Clock \"clk\" has Internal fmax of 96.21 MHz between source register \"dds:inst\|dds_m\[5\]\" and destination register \"dds:inst\|dds_add\[9\]\" (period= 10.394 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.950 ns + Longest register register " "Info: + Longest register to register delay is 4.950 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:inst\|dds_m\[5\] 1 REG LC_X3_Y2_N5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'dds:inst\|dds_m\[5\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:inst|dds_m[5] } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 144 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.055 ns) + CELL(0.747 ns) 2.802 ns dds:inst\|dds_add\[5\]~148 2 COMB LC_X5_Y2_N7 2 " "Info: 2: + IC(2.055 ns) + CELL(0.747 ns) = 2.802 ns; Loc. = LC_X5_Y2_N7; Fanout = 2; COMB Node = 'dds:inst\|dds_add\[5\]~148'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.802 ns" { dds:inst|dds_m[5] dds:inst|dds_add[5]~148 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.925 ns dds:inst\|dds_add\[6\]~147 3 COMB LC_X5_Y2_N8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.925 ns; Loc. = LC_X5_Y2_N8; Fanout = 2; COMB Node = 'dds:inst\|dds_add\[6\]~147'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { dds:inst|dds_add[5]~148 dds:inst|dds_add[6]~147 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 3.324 ns dds:inst\|dds_add\[7\]~146 4 COMB LC_X5_Y2_N9 6 " "Info: 4: + IC(0.000 ns) + CELL(0.399 ns) = 3.324 ns; Loc. = LC_X5_Y2_N9; Fanout = 6; COMB Node = 'dds:inst\|dds_add\[7\]~146'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.399 ns" { dds:inst|dds_add[6]~147 dds:inst|dds_add[7]~146 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 4.950 ns dds:inst\|dds_add\[9\] 5 REG LC_X6_Y2_N1 30 " "Info: 5: + IC(0.000 ns) + CELL(1.626 ns) = 4.950 ns; Loc. = LC_X6_Y2_N1; Fanout = 30; REG Node = 'dds:inst\|dds_add\[9\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.626 ns" { dds:inst|dds_add[7]~146 dds:inst|dds_add[9] } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.895 ns ( 58.48 % ) " "Info: Total cell delay = 2.895 ns ( 58.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.055 ns ( 41.52 % ) " "Info: Total interconnect delay = 2.055 ns ( 41.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.950 ns" { dds:inst|dds_m[5] dds:inst|dds_add[5]~148 dds:inst|dds_add[6]~147 dds:inst|dds_add[7]~146 dds:inst|dds_add[9] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "4.950 ns" { dds:inst|dds_m[5] dds:inst|dds_add[5]~148 dds:inst|dds_add[6]~147 dds:inst|dds_add[7]~146 dds:inst|dds_add[9] } { 0.000ns 2.055ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.747ns 0.123ns 0.399ns 1.626ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.735 ns - Smallest " "Info: - Smallest clock skew is -4.735 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.388 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 80 -32 136 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns dds:inst\|cp_65k 2 REG LC_X2_Y3_N4 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N4; Fanout = 25; REG Node = 'dds:inst\|cp_65k'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk dds:inst|cp_65k } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 7.388 ns dds:inst\|dds_add\[9\] 3 REG LC_X6_Y2_N1 30 " "Info: 3: + IC(2.746 ns) + CELL(0.918 ns) = 7.388 ns; Loc. = LC_X6_Y2_N1; Fanout = 30; REG Node = 'dds:inst\|dds_add\[9\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.664 ns" { dds:inst|cp_65k dds:inst|dds_add[9] } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.68 % ) " "Info: Total cell delay = 3.375 ns ( 45.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.013 ns ( 54.32 % ) " "Info: Total interconnect delay = 4.013 ns ( 54.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.388 ns" { clk dds:inst|cp_65k dds:inst|dds_add[9] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "7.388 ns" { clk clk~combout dds:inst|cp_65k dds:inst|dds_add[9] } { 0.000ns 0.000ns 1.267ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.123 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.123 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 80 -32 136 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns dds:inst\|cp_65k 2 REG LC_X2_Y3_N4 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N4; Fanout = 25; REG Node = 'dds:inst\|cp_65k'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk dds:inst|cp_65k } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.764 ns dds:inst\|cp_1k 3 REG LC_X2_Y2_N0 12 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.764 ns; Loc. = LC_X2_Y2_N0; Fanout = 12; REG Node = 'dds:inst\|cp_1k'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.040 ns" { dds:inst|cp_65k dds:inst|cp_1k } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.441 ns) + CELL(0.918 ns) 12.123 ns dds:inst\|dds_m\[5\] 4 REG LC_X3_Y2_N5 8 " "Info: 4: + IC(3.441 ns) + CELL(0.918 ns) = 12.123 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'dds:inst\|dds_m\[5\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.359 ns" { dds:inst|cp_1k dds:inst|dds_m[5] } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 144 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 38.51 % ) " "Info: Total cell delay = 4.669 ns ( 38.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.454 ns ( 61.49 % ) " "Info: Total interconnect delay = 7.454 ns ( 61.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "12.123 ns" { clk dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "12.123 ns" { clk clk~combout dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } { 0.000ns 0.000ns 1.267ns 2.746ns 3.441ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.388 ns" { clk dds:inst|cp_65k dds:inst|dds_add[9] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "7.388 ns" { clk clk~combout dds:inst|cp_65k dds:inst|dds_add[9] } { 0.000ns 0.000ns 1.267ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "12.123 ns" { clk dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "12.123 ns" { clk clk~combout dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } { 0.000ns 0.000ns 1.267ns 2.746ns 3.441ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 144 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.950 ns" { dds:inst|dds_m[5] dds:inst|dds_add[5]~148 dds:inst|dds_add[6]~147 dds:inst|dds_add[7]~146 dds:inst|dds_add[9] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "4.950 ns" { dds:inst|dds_m[5] dds:inst|dds_add[5]~148 dds:inst|dds_add[6]~147 dds:inst|dds_add[7]~146 dds:inst|dds_add[9] } { 0.000ns 2.055ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.747ns 0.123ns 0.399ns 1.626ns } "" } } { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.388 ns" { clk dds:inst|cp_65k dds:inst|dds_add[9] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "7.388 ns" { clk clk~combout dds:inst|cp_65k dds:inst|dds_add[9] } { 0.000ns 0.000ns 1.267ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "12.123 ns" { clk dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "12.123 ns" { clk clk~combout dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } { 0.000ns 0.000ns 1.267ns 2.746ns 3.441ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}