atmega16.tan.summary

来自「基于FPGA的DDS正弦信号发生器,信号失真小」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -0.293 ns
From           : key[0]
To             : dds:inst|dds_m[5]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.992 ns
From           : dds:inst|dds_add[12]
To             : datap[0]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 5.705 ns
From           : key[1]
To             : dds:inst|bell
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 96.21 MHz ( period = 10.394 ns )
From           : dds:inst|dds_m[5]
To             : dds:inst|dds_add[10]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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