atmega16.fit.qmsg

基于FPGA的DDS正弦信号发生器,信号失真小

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "12.649 ns register pin " "Info: Estimated most critical path is register to pin delay of 12.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:inst\|dds_add\[10\] 1 REG LAB_X6_Y2 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y2; Fanout = 33; REG Node = 'dds:inst\|dds_add\[10\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:inst|dds_add[10] } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.557 ns) + CELL(0.200 ns) 1.757 ns dds:inst\|Mux26~359 2 COMB LAB_X7_Y2 2 " "Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X7_Y2; Fanout = 2; COMB Node = 'dds:inst\|Mux26~359'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.757 ns" { dds:inst|dds_add[10] dds:inst|Mux26~359 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.766 ns) + CELL(0.511 ns) 4.034 ns dds:inst\|Mux26~362 3 COMB LAB_X6_Y1 2 " "Info: 3: + IC(1.766 ns) + CELL(0.511 ns) = 4.034 ns; Loc. = LAB_X6_Y1; Fanout = 2; COMB Node = 'dds:inst\|Mux26~362'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.277 ns" { dds:inst|Mux26~359 dds:inst|Mux26~362 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.074 ns) + CELL(0.200 ns) 6.308 ns dds:inst\|Mux26~363 4 COMB LAB_X7_Y2 1 " "Info: 4: + IC(2.074 ns) + CELL(0.200 ns) = 6.308 ns; Loc. = LAB_X7_Y2; Fanout = 1; COMB Node = 'dds:inst\|Mux26~363'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.274 ns" { dds:inst|Mux26~362 dds:inst|Mux26~363 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.537 ns) + CELL(0.740 ns) 8.585 ns dds:inst\|Mux26~365 5 COMB LAB_X6_Y1 1 " "Info: 5: + IC(1.537 ns) + CELL(0.740 ns) = 8.585 ns; Loc. = LAB_X6_Y1; Fanout = 1; COMB Node = 'dds:inst\|Mux26~365'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.277 ns" { dds:inst|Mux26~363 dds:inst|Mux26~365 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.742 ns) + CELL(2.322 ns) 12.649 ns datap\[0\] 6 PIN PIN_40 0 " "Info: 6: + IC(1.742 ns) + CELL(2.322 ns) = 12.649 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'datap\[0\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.064 ns" { dds:inst|Mux26~365 datap[0] } "NODE_NAME" } } { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 80 376 552 96 "datap\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.973 ns ( 31.41 % ) " "Info: Total cell delay = 3.973 ns ( 31.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.676 ns ( 68.59 % ) " "Info: Total interconnect delay = 8.676 ns ( 68.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "12.649 ns" { dds:inst|dds_add[10] dds:inst|Mux26~359 dds:inst|Mux26~362 dds:inst|Mux26~363 dds:inst|Mux26~365 datap[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "9 9 " "Info: Average interconnect usage is 9% of the available device resources. Peak interconnect usage is 9%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y5 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "cs GND " "Info: Pin cs has GND driving its datain port" {  } { { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 96 376 552 112 "cs" "" } } } } { "d:/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cs" } } } } { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cs } "NODE_NAME" } } { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cs } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Info: Allocated 160 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 06 13:02:13 2008 " "Info: Processing ended: Thu Nov 06 13:02:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/王振宇/CPLD/我的程序/dds综合/atmega16.fit.smsg " "Info: Generated suppressed messages file F:/王振宇/CPLD/我的程序/dds综合/atmega16.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}