adder8.fit.rpt

来自「通过VHDL实现4位全加器」· RPT 代码 · 共 517 行 · 第 1/5 页

Fitter report for adder8
Thu Nov 27 22:35:32 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Non-Global High Fan-Out Signals
 15. Interconnect Usage Summary
 16. LAB Logic Elements
 17. LAB Distinct Inputs
 18. I/O Rules Summary
 19. I/O Rules Details
 20. I/O Rules Matrix
 21. Fitter Device Options
 22. Operating Settings and Conditions
 23. Advanced Data - General
 24. Advanced Data - Placement Preparation
 25. Advanced Data - Placement
 26. Advanced Data - Routing
 27. Fitter Messages
 28. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Fitter Summary                                                          ;
+-------------------------------+-----------------------------------------+
; Fitter Status                 ; Successful - Thu Nov 27 22:35:32 2008   ;
; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name                 ; adder8                                  ;
; Top-level Entity Name         ; adder8                                  ;
; Family                        ; Stratix II                              ;
; Device                        ; EP2S15F484C3                            ;
; Timing Models                 ; Final                                   ;
; Logic utilization             ; < 1 %                                   ;
;     Combinational ALUTs       ; 9 / 12,480 ( < 1 % )                    ;
;     Dedicated logic registers ; 0 / 12,480 ( 0 % )                      ;
; Total registers               ; 0                                       ;
; Total pins                    ; 26 / 343 ( 8 % )                        ;
; Total virtual pins            ; 0                                       ;
; Total block memory bits       ; 0 / 419,328 ( 0 % )                     ;
; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                          ;
; Total PLLs                    ; 0 / 6 ( 0 % )                           ;
; Total DLLs                    ; 0 / 2 ( 0 % )                           ;
+-------------------------------+-----------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; AUTO                           ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;