adder8.vhd

来自「通过VHDL实现4位全加器」· VHDL 代码 · 共 20 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY adder8 IS
	GENERIC(delay_sum,delay_cout:TIME:=1ns);
	PORT(cin:IN STD_LOGIC;
		a,b:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		sum:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		cout:OUT STD_LOGIC);
END adder8;
ARCHITECTURE one of adder8 IS
SIGNAL SINT:STD_LOGIC_VECTOR(8 DOWNTO 0);
	SIGNAL AA,BB:STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
	AA<='0'&a(7 DOWNTO 0);
	BB<='0'&b(7 DOWNTO 0);
	SINT<=AA+BB+CIN;
	sum(7 DOWNTO 0)<=SINT(7 DOWNTO 0) AFTER delay_sum;
	cout<=SINT(8) AFTER delay_cout;
END one;