adder8.map.rpt

来自「通过VHDL实现4位全加器」· RPT 代码 · 共 236 行 · 第 1/2 页

; Retiming Meta-Stability Register Sequence Length                            ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                ; Normal compilation ; Normal compilation ;
; HDL message level                                                           ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                             ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                    ; 100                ; 100                ;
; Clock MUX Protection                                                        ; On                 ; On                 ;
; Block Design Naming                                                         ; Auto               ; Auto               ;
+-----------------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                      ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                         ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
; adder8.vhd                       ; yes             ; User VHDL File  ; F:/Engineering Document/Quartus7.2/adder8/adder8.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 9     ;
; Dedicated logic registers                     ; 0     ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 0     ;
;                                               ;       ;
; Total combinational functions                 ; 9     ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 0     ;
;     -- 6 input functions                      ; 0     ;
;     -- 5 input functions                      ; 0     ;
;     -- 4 input functions                      ; 0     ;
;     -- <=3 input functions                    ; 9     ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 0     ;
;     -- extended LUT mode                      ; 0     ;
;     -- arithmetic mode                        ; 0     ;
;     -- shared arithmetic mode                 ; 9     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 9     ;
;                                               ;       ;
; Total registers                               ; 0     ;
;     -- Dedicated logic registers              ; 0     ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 5     ;
;                                               ;       ;
; I/O pins                                      ; 26    ;
; Maximum fan-out node                          ; _~1   ;
; Maximum fan-out                               ; 2     ;
; Total fan-out                                 ; 34    ;
; Average fan-out                               ; 0.97  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |adder8                    ; 9 (9)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 26   ; 0            ; |adder8             ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |adder8 ;
+----------------+------------+------------------------------------------+
; Parameter Name ; Value      ; Type                                     ;
+----------------+------------+------------------------------------------+
; delay_sum      ; 1000000 fs ; Physical                                 ;
; delay_cout     ; 1000000 fs ; Physical                                 ;
+----------------+------------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Thu Nov 27 22:35:25 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder8 -c adder8
Info: Found 2 design units, including 1 entities, in source file adder8.vhd
    Info: Found design unit 1: adder8-one
    Info: Found entity 1: adder8
Info: Elaborating entity "adder8" for the top level hierarchy
Info: Implemented 35 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 9 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 170 megabytes of memory during processing
    Info: Processing ended: Thu Nov 27 22:35:26 2008
    Info: Elapsed time: 00:00:01