adder4.vhd.bak

来自「通过VHDL实现4位全加器」· BAK 代码 · 共 19 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY adder4 IS
	PORT(cin:IN STD_LOGIC;
		a,b:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		sum:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		cout:OUT STD_LOGIC);
END adder4;
ARCHITECTURE one of adder4 IS
SIGNAL SINT:STD_LOGIC_VECTOR(4 DOWNTO 0);
	SIGNAL AA,BB:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
	AA<='0'&a(3 DOWNTO 0);
	BB<='0'&a(3 DOWNTO 0);
	SINT<=A'A+BB+CIN;
	sum(3 DOWNTO 0)<=SINT(3 DOWNTO 0);
	cout<=SINT(4);
END one;