adder4.map.summary

来自「通过VHDL实现4位全加器」· SUMMARY 代码 · 共 16 行

Analysis & Synthesis Status : Successful - Sat Nov 15 23:25:02 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Web Edition
Revision Name : adder4
Top-level Entity Name : adder4
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 5
    Dedicated logic registers : 0
Total registers : 0
Total pins : 14
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0