adder4.tan.rpt

来自「通过VHDL实现4位全加器」· RPT 代码 · 共 136 行

Classic Timing Analyzer report for adder4
Sat Nov 15 23:25:17 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 10.261 ns   ; a[3] ; cout ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;      ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------+
; tpd                                                         ;
+-------+-------------------+-----------------+------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To     ;
+-------+-------------------+-----------------+------+--------+
; N/A   ; None              ; 10.261 ns       ; a[3] ; cout   ;
; N/A   ; None              ; 10.049 ns       ; a[2] ; cout   ;
; N/A   ; None              ; 9.975 ns        ; a[0] ; cout   ;
; N/A   ; None              ; 9.918 ns        ; b[3] ; cout   ;
; N/A   ; None              ; 9.902 ns        ; b[1] ; cout   ;
; N/A   ; None              ; 9.865 ns        ; cin  ; cout   ;
; N/A   ; None              ; 9.831 ns        ; b[0] ; cout   ;
; N/A   ; None              ; 9.755 ns        ; a[1] ; cout   ;
; N/A   ; None              ; 9.739 ns        ; b[2] ; cout   ;
; N/A   ; None              ; 8.517 ns        ; a[0] ; sum[0] ;
; N/A   ; None              ; 8.402 ns        ; cin  ; sum[0] ;
; N/A   ; None              ; 8.355 ns        ; b[0] ; sum[0] ;
; N/A   ; None              ; 8.149 ns        ; a[3] ; sum[3] ;
; N/A   ; None              ; 7.995 ns        ; a[2] ; sum[3] ;
; N/A   ; None              ; 7.983 ns        ; a[0] ; sum[1] ;
; N/A   ; None              ; 7.907 ns        ; a[2] ; sum[2] ;
; N/A   ; None              ; 7.899 ns        ; a[0] ; sum[3] ;
; N/A   ; None              ; 7.873 ns        ; cin  ; sum[1] ;
; N/A   ; None              ; 7.847 ns        ; a[0] ; sum[2] ;
; N/A   ; None              ; 7.844 ns        ; b[1] ; sum[1] ;
; N/A   ; None              ; 7.839 ns        ; b[0] ; sum[1] ;
; N/A   ; None              ; 7.826 ns        ; b[1] ; sum[3] ;
; N/A   ; None              ; 7.794 ns        ; b[1] ; sum[2] ;
; N/A   ; None              ; 7.793 ns        ; b[3] ; sum[3] ;
; N/A   ; None              ; 7.789 ns        ; cin  ; sum[3] ;
; N/A   ; None              ; 7.755 ns        ; b[0] ; sum[3] ;
; N/A   ; None              ; 7.737 ns        ; cin  ; sum[2] ;
; N/A   ; None              ; 7.703 ns        ; b[0] ; sum[2] ;
; N/A   ; None              ; 7.679 ns        ; a[1] ; sum[3] ;
; N/A   ; None              ; 7.678 ns        ; a[1] ; sum[1] ;
; N/A   ; None              ; 7.677 ns        ; b[2] ; sum[3] ;
; N/A   ; None              ; 7.641 ns        ; a[1] ; sum[2] ;
; N/A   ; None              ; 7.576 ns        ; b[2] ; sum[2] ;
+-------+-------------------+-----------------+------+--------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Sat Nov 15 23:25:17 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder4 -c adder4 --timing_analysis_only
Info: Longest tpd from source pin "a[3]" to destination pin "cout" is 10.261 ns
    Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_Y21; Fanout = 3; PIN Node = 'a[3]'
    Info: 2: + IC(4.129 ns) + CELL(0.378 ns) = 5.347 ns; Loc. = LCCOMB_X25_Y1_N22; Fanout = 1; COMB Node = '_~15'
    Info: 3: + IC(0.000 ns) + CELL(0.312 ns) = 5.659 ns; Loc. = LCCOMB_X25_Y1_N24; Fanout = 1; COMB Node = '_~17'
    Info: 4: + IC(2.556 ns) + CELL(2.046 ns) = 10.261 ns; Loc. = PIN_B10; Fanout = 0; PIN Node = 'cout'
    Info: Total cell delay = 3.576 ns ( 34.85 % )
    Info: Total interconnect delay = 6.685 ns ( 65.15 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Allocated 133 megabytes of memory during processing
    Info: Processing ended: Sat Nov 15 23:25:18 2008
    Info: Elapsed time: 00:00:01