reg8.tan.qmsg

来自「通过VHDL实现4位全加器」· QMSG 代码 · 共 10 行 · 第 1/3 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register int_reg\[0\] int_reg\[6\] 500.0 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 500.0 MHz between source register \"int_reg\[0\]\" and destination register \"int_reg\[6\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.476 ns + Longest register register " "Info: + Longest register to register delay is 1.476 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_reg\[0\] 1 REG LCFF_X31_Y4_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y4_N1; Fanout = 5; REG Node = 'int_reg\[0\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_reg[0] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.309 ns) 0.564 ns Add0~250 2 COMB LCCOMB_X31_Y4_N16 2 " "Info: 2: + IC(0.255 ns) + CELL(0.309 ns) = 0.564 ns; Loc. = LCCOMB_X31_Y4_N16; Fanout = 2; COMB Node = 'Add0~250'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.564 ns" { int_reg[0] Add0~250 } "NODE_NAME" } } { "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.599 ns Add0~254 3 COMB LCCOMB_X31_Y4_N18 2 " "Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.599 ns; Loc. = LCCOMB_X31_Y4_N18; Fanout = 2; COMB Node = 'Add0~254'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~250 Add0~254 } "NODE_NAME" } } { "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.634 ns Add0~258 4 COMB LCCOMB_X31_Y4_N20 2 " "Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 0.634 ns; Loc. = LCCOMB_X31_Y4_N20; Fanout = 2; COMB Node = 'Add0~258'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~254 Add0~258 } "NODE_NAME" } } { "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.669 ns Add0~262 5 COMB LCCOMB_X31_Y4_N22 2 " "Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 0.669 ns; Loc. = LCCOMB_X31_Y4_N22; Fanout = 2; COMB Node = 'Add0~262'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~258 Add0~262 } "NODE_NAME" } } { "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.704 ns Add0~266 6 COMB LCCOMB_X31_Y4_N24 2 " "Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 0.704 ns; Loc. = LCCOMB_X31_Y4_N24; Fanout = 2; COMB Node = 'Add0~266'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~262 Add0~266 } "NODE_NAME" } } { "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.739 ns Add0~270 7 COMB LCCOMB_X31_Y4_N26 2 " "Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 0.739 ns; Loc. = LCCOMB_X31_Y4_N26; Fanout = 2; COMB Node = 'Add0~270'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~266 Add0~270 } "NODE_NAME" } } { "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 0.864 ns Add0~273 8 COMB LCCOMB_X31_Y4_N28 2 " "Info: 8: + IC(0.000 ns) + CELL(0.125 ns) = 0.864 ns; Loc. = LCCOMB_X31_Y4_N28; Fanout = 2; COMB Node = 'Add0~273'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { Add0~270 Add0~273 } "NODE_NAME" } } { "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/program/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.053 ns) 1.321 ns Mux1~17 9 COMB LCCOMB_X31_Y4_N4 1 " "Info: 9: + IC(0.404 ns) + CELL(0.053 ns) = 1.321 ns; Loc. = LCCOMB_X31_Y4_N4; Fanout = 1; COMB Node = 'Mux1~17'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.457 ns" { Add0~273 Mux1~17 } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.476 ns int_reg\[6\] 10 REG LCFF_X31_Y4_N5 5 " "Info: 10: + IC(0.000 ns) + CELL(0.155 ns) = 1.476 ns; Loc. = LCFF_X31_Y4_N5; Fanout = 5; REG Node = 'int_reg\[6\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Mux1~17 int_reg[6] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.817 ns ( 55.35 % ) " "Info: Total cell delay = 0.817 ns ( 55.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.659 ns ( 44.65 % ) " "Info: Total interconnect delay = 0.659 ns ( 44.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.476 ns" { int_reg[0] Add0~250 Add0~254 Add0~258 Add0~262 Add0~266 Add0~270 Add0~273 Mux1~17 int_reg[6] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "1.476 ns" { int_reg[0] {} Add0~250 {} Add0~254 {} Add0~258 {} Add0~262 {} Add0~266 {} Add0~270 {} Add0~273 {} Mux1~17 {} int_reg[6] {} } { 0.000ns 0.255ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.404ns 0.000ns } { 0.000ns 0.309ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.125ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.484 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns int_reg\[6\] 3 REG LCFF_X31_Y4_N5 5 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X31_Y4_N5; Fanout = 5; REG Node = 'int_reg\[6\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { clock~clkctrl int_reg[6] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl int_reg[6] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[6] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.484 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns int_reg\[0\] 3 REG LCFF_X31_Y4_N1 5 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X31_Y4_N1; Fanout = 5; REG Node = 'int_reg\[0\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { clock~clkctrl int_reg[0] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl int_reg[0] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[0] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl int_reg[6] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[6] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl int_reg[0] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[0] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.476 ns" { int_reg[0] Add0~250 Add0~254 Add0~258 Add0~262 Add0~266 Add0~270 Add0~273 Mux1~17 int_reg[6] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "1.476 ns" { int_reg[0] {} Add0~250 {} Add0~254 {} Add0~258 {} Add0~262 {} Add0~266 {} Add0~270 {} Add0~273 {} Mux1~17 {} int_reg[6] {} } { 0.000ns 0.255ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.404ns 0.000ns } { 0.000ns 0.309ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.125ns 0.053ns 0.155ns } "" } } { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl int_reg[6] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[6] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl int_reg[0] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[0] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_reg[6] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { int_reg[6] {} } {  } {  } "" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "int_reg\[3\] mode\[2\] clock 3.782 ns register " "Info: tsu for register \"int_reg\[3\]\" (data pin = \"mode\[2\]\", clock pin = \"clock\") is 3.782 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.173 ns + Longest pin register " "Info: + Longest pin to register delay is 6.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.847 ns) 0.847 ns mode\[2\] 1 PIN PIN_Y8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.847 ns) = 0.847 ns; Loc. = PIN_Y8; Fanout = 3; PIN Node = 'mode\[2\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode[2] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.835 ns) + CELL(0.366 ns) 5.048 ns int_reg\[0\]~132 2 COMB LCCOMB_X30_Y4_N28 10 " "Info: 2: + IC(3.835 ns) + CELL(0.366 ns) = 5.048 ns; Loc. = LCCOMB_X30_Y4_N28; Fanout = 10; COMB Node = 'int_reg\[0\]~132'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.201 ns" { mode[2] int_reg[0]~132 } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.592 ns) + CELL(0.378 ns) 6.018 ns Mux4~17 3 COMB LCCOMB_X30_Y4_N4 1 " "Info: 3: + IC(0.592 ns) + CELL(0.378 ns) = 6.018 ns; Loc. = LCCOMB_X30_Y4_N4; Fanout = 1; COMB Node = 'Mux4~17'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.970 ns" { int_reg[0]~132 Mux4~17 } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 6.173 ns int_reg\[3\] 4 REG LCFF_X30_Y4_N5 6 " "Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 6.173 ns; Loc. = LCFF_X30_Y4_N5; Fanout = 6; REG Node = 'int_reg\[3\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Mux4~17 int_reg[3] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.746 ns ( 28.28 % ) " "Info: Total cell delay = 1.746 ns ( 28.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.427 ns ( 71.72 % ) " "Info: Total interconnect delay = 4.427 ns ( 71.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.173 ns" { mode[2] int_reg[0]~132 Mux4~17 int_reg[3] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "6.173 ns" { mode[2] {} mode[2]~combout {} int_reg[0]~132 {} Mux4~17 {} int_reg[3] {} } { 0.000ns 0.000ns 3.835ns 0.592ns 0.000ns } { 0.000ns 0.847ns 0.366ns 0.378ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.481 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 2.481 ns int_reg\[3\] 3 REG LCFF_X30_Y4_N5 6 " "Info: 3: + IC(0.666 ns) + CELL(0.618 ns) = 2.481 ns; Loc. = LCFF_X30_Y4_N5; Fanout = 6; REG Node = 'int_reg\[3\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { clock~clkctrl int_reg[3] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.33 % ) " "Info: Total cell delay = 1.472 ns ( 59.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 40.67 % ) " "Info: Total interconnect delay = 1.009 ns ( 40.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clock clock~clkctrl int_reg[3] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[3] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.173 ns" { mode[2] int_reg[0]~132 Mux4~17 int_reg[3] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "6.173 ns" { mode[2] {} mode[2]~combout {} int_reg[0]~132 {} Mux4~17 {} int_reg[3] {} } { 0.000ns 0.000ns 3.835ns 0.592ns 0.000ns } { 0.000ns 0.847ns 0.366ns 0.378ns 0.155ns } "" } } { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clock clock~clkctrl int_reg[3] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[3] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock termcnt int_reg\[6\] 6.492 ns register " "Info: tco from clock \"clock\" to destination pin \"termcnt\" through register \"int_reg\[6\]\" is 6.492 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.484 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns int_reg\[6\] 3 REG LCFF_X31_Y4_N5 5 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X31_Y4_N5; Fanout = 5; REG Node = 'int_reg\[6\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { clock~clkctrl int_reg[6] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl int_reg[6] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[6] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.914 ns + Longest register pin " "Info: + Longest register to pin delay is 3.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_reg\[6\] 1 REG LCFF_X31_Y4_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y4_N5; Fanout = 5; REG Node = 'int_reg\[6\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_reg[6] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.228 ns) 0.788 ns det_zero~38 2 COMB LCCOMB_X30_Y4_N26 1 " "Info: 2: + IC(0.560 ns) + CELL(0.228 ns) = 0.788 ns; Loc. = LCCOMB_X30_Y4_N26; Fanout = 1; COMB Node = 'det_zero~38'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.788 ns" { int_reg[6] det_zero~38 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.202 ns) + CELL(0.053 ns) 1.043 ns det_zero~6 3 COMB LCCOMB_X30_Y4_N30 1 " "Info: 3: + IC(0.202 ns) + CELL(0.053 ns) = 1.043 ns; Loc. = LCCOMB_X30_Y4_N30; Fanout = 1; COMB Node = 'det_zero~6'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.255 ns" { det_zero~38 det_zero~6 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(1.982 ns) 3.914 ns termcnt 4 PIN PIN_AB7 0 " "Info: 4: + IC(0.889 ns) + CELL(1.982 ns) = 3.914 ns; Loc. = PIN_AB7; Fanout = 0; PIN Node = 'termcnt'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { det_zero~6 termcnt } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.263 ns ( 57.82 % ) " "Info: Total cell delay = 2.263 ns ( 57.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.651 ns ( 42.18 % ) " "Info: Total interconnect delay = 1.651 ns ( 42.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { int_reg[6] det_zero~38 det_zero~6 termcnt } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { int_reg[6] {} det_zero~38 {} det_zero~6 {} termcnt {} } { 0.000ns 0.560ns 0.202ns 0.889ns } { 0.000ns 0.228ns 0.053ns 1.982ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clock clock~clkctrl int_reg[6] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[6] {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { int_reg[6] det_zero~38 det_zero~6 termcnt } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.914 ns" { int_reg[6] {} det_zero~38 {} det_zero~6 {} termcnt {} } { 0.000ns 0.560ns 0.202ns 0.889ns } { 0.000ns 0.228ns 0.053ns 1.982ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "int_reg\[5\] datain\[5\] clock -2.286 ns register " "Info: th for register \"int_reg\[5\]\" (data pin = \"datain\[5\]\", clock pin = \"clock\") is -2.286 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.481 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clock 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clock~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 2.481 ns int_reg\[5\] 3 REG LCFF_X30_Y4_N21 3 " "Info: 3: + IC(0.666 ns) + CELL(0.618 ns) = 2.481 ns; Loc. = LCFF_X30_Y4_N21; Fanout = 3; REG Node = 'int_reg\[5\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { clock~clkctrl int_reg[5] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.33 % ) " "Info: Total cell delay = 1.472 ns ( 59.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 40.67 % ) " "Info: Total interconnect delay = 1.009 ns ( 40.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clock clock~clkctrl int_reg[5] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[5] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.916 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.847 ns) 0.847 ns datain\[5\] 1 PIN PIN_Y7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.847 ns) = 0.847 ns; Loc. = PIN_Y7; Fanout = 2; PIN Node = 'datain\[5\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { datain[5] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.760 ns) + CELL(0.154 ns) 4.761 ns Mux2~17 2 COMB LCCOMB_X30_Y4_N20 1 " "Info: 2: + IC(3.760 ns) + CELL(0.154 ns) = 4.761 ns; Loc. = LCCOMB_X30_Y4_N20; Fanout = 1; COMB Node = 'Mux2~17'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.914 ns" { datain[5] Mux2~17 } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.916 ns int_reg\[5\] 3 REG LCFF_X30_Y4_N21 3 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.916 ns; Loc. = LCFF_X30_Y4_N21; Fanout = 3; REG Node = 'int_reg\[5\]'" {  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Mux2~17 int_reg[5] } "NODE_NAME" } } { "reg8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register8/reg8.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.156 ns ( 23.52 % ) " "Info: Total cell delay = 1.156 ns ( 23.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.760 ns ( 76.48 % ) " "Info: Total interconnect delay = 3.760 ns ( 76.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { datain[5] Mux2~17 int_reg[5] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "4.916 ns" { datain[5] {} datain[5]~combout {} Mux2~17 {} int_reg[5] {} } { 0.000ns 0.000ns 3.760ns 0.000ns } { 0.000ns 0.847ns 0.154ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clock clock~clkctrl int_reg[5] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clock {} clock~combout {} clock~clkctrl {} int_reg[5] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { datain[5] Mux2~17 int_reg[5] } "NODE_NAME" } } { "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "4.916 ns" { datain[5] {} datain[5]~combout {} Mux2~17 {} int_reg[5] {} } { 0.000ns 0.000ns 3.760ns 0.000ns } { 0.000ns 0.847ns 0.154ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}