reg8.hier_info

来自「通过VHDL实现4位全加器」· HIER_INFO 代码 · 共 55 行

|reg8
clock => int_reg[7].CLK
clock => int_reg[6].CLK
clock => int_reg[5].CLK
clock => int_reg[4].CLK
clock => int_reg[3].CLK
clock => int_reg[2].CLK
clock => int_reg[1].CLK
clock => int_reg[0].CLK
serinl => Mux7.IN3
serinr => Mux0.IN3
mode[0] => Mux7.IN6
mode[0] => Mux6.IN5
mode[0] => Mux5.IN5
mode[0] => Mux4.IN5
mode[0] => Mux3.IN5
mode[0] => Mux2.IN5
mode[0] => Mux1.IN5
mode[0] => Mux0.IN6
mode[1] => Mux7.IN5
mode[1] => Mux6.IN4
mode[1] => Mux5.IN4
mode[1] => Mux4.IN4
mode[1] => Mux3.IN4
mode[1] => Mux2.IN4
mode[1] => Mux1.IN4
mode[1] => Mux0.IN5
mode[2] => Mux7.IN4
mode[2] => Mux6.IN3
mode[2] => Mux5.IN3
mode[2] => Mux4.IN3
mode[2] => Mux3.IN3
mode[2] => Mux2.IN3
mode[2] => Mux1.IN3
mode[2] => Mux0.IN4
datain[0] => Mux7.IN7
datain[1] => Mux6.IN6
datain[2] => Mux5.IN6
datain[3] => Mux4.IN6
datain[4] => Mux3.IN6
datain[5] => Mux2.IN6
datain[6] => Mux1.IN6
datain[7] => Mux0.IN7
dataout[0] <= int_reg[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= int_reg[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= int_reg[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= int_reg[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= int_reg[4].DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= int_reg[5].DB_MAX_OUTPUT_PORT_TYPE
dataout[6] <= int_reg[6].DB_MAX_OUTPUT_PORT_TYPE
dataout[7] <= int_reg[7].DB_MAX_OUTPUT_PORT_TYPE
termcnt <= det_zero~6.DB_MAX_OUTPUT_PORT_TYPE