prev_cmp_register-8.qmsg

通过VHDL实现4位全加器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Web Edition " "Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 21 15:37:33 2008 " "Info: Processing started: Fri Nov 21 15:37:33 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off register-8 -c register-8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off register-8 -c register-8" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "register-8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file register-8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 unicntr-v1 " "Info: Found design unit 1: unicntr-v1" {  } { { "register-8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register-8/register-8.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 register8 " "Info: Found entity 1: register8" {  } { { "register-8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register-8/register-8.vhd" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_UNCOMPILED_ENTITY" "unicntr register-8.vhd(21) " "Error (10334): VHDL error at register-8.vhd(21): entity \"unicntr\" is used but not declared" {  } { { "register-8.vhd" "" { Text "F:/Engineering Document/Quartus7.2/register-8/register-8.vhd" 21 0 0 } }  } 0 10334 "VHDL error at %2!s!: entity \"%1!s!\" is used but not declared" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Nov 21 15:37:34 2008 " "Error: Processing ended: Fri Nov 21 15:37:34 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 1  0 s " "Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}