reg8.fit.summary

通过VHDL实现4位全加器

Fitter Status : Successful - Sun Dec 07 12:31:55 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Web Edition
Revision Name : reg8
Top-level Entity Name : reg8
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : < 1 %
    Combinational ALUTs : 24 / 12,480 ( < 1 % )
    Dedicated logic registers : 10 / 12,480 ( < 1 % )
Total registers : 10
Total pins : 23 / 343 ( 7 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )