reg8.inc

来自「通过VHDL实现4位全加器」· INC 代码 · 共 26 行

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-- Generated by Quartus II Version 7.2 (Build Build 151 09/26/2007)
-- Created on Sun Dec 07 14:25:14 2008

FUNCTION reg8 (clock, serinl, serinr, mode[2..0], datain[7..0])
	WITH (n)
	RETURNS (dataout[7..0], termcnt);