reg8.tan.rpt

通过VHDL实现4位全加器

; N/A           ; None        ; -2.878 ns ; mode[2]   ; int_reg[5]           ; clock    ;
; N/A           ; None        ; -2.878 ns ; mode[2]   ; int_reg[5]~DUPLICATE ; clock    ;
; N/A           ; None        ; -2.975 ns ; mode[2]   ; int_reg[0]           ; clock    ;
; N/A           ; None        ; -2.975 ns ; mode[2]   ; int_reg[1]           ; clock    ;
; N/A           ; None        ; -2.975 ns ; mode[2]   ; int_reg[6]~DUPLICATE ; clock    ;
; N/A           ; None        ; -2.975 ns ; mode[2]   ; int_reg[7]           ; clock    ;
; N/A           ; None        ; -2.975 ns ; mode[2]   ; int_reg[6]           ; clock    ;
; N/A           ; None        ; -3.034 ns ; mode[0]   ; int_reg[7]           ; clock    ;
; N/A           ; None        ; -3.036 ns ; mode[0]   ; int_reg[1]           ; clock    ;
; N/A           ; None        ; -3.037 ns ; mode[0]   ; int_reg[6]~DUPLICATE ; clock    ;
; N/A           ; None        ; -3.037 ns ; mode[0]   ; int_reg[6]           ; clock    ;
; N/A           ; None        ; -3.038 ns ; mode[0]   ; int_reg[0]           ; clock    ;
; N/A           ; None        ; -3.059 ns ; mode[1]   ; int_reg[2]           ; clock    ;
; N/A           ; None        ; -3.059 ns ; mode[1]   ; int_reg[3]           ; clock    ;
; N/A           ; None        ; -3.059 ns ; mode[1]   ; int_reg[4]           ; clock    ;
; N/A           ; None        ; -3.059 ns ; mode[1]   ; int_reg[5]           ; clock    ;
; N/A           ; None        ; -3.059 ns ; mode[1]   ; int_reg[5]~DUPLICATE ; clock    ;
; N/A           ; None        ; -3.065 ns ; mode[1]   ; int_reg[0]           ; clock    ;
; N/A           ; None        ; -3.108 ns ; mode[0]   ; int_reg[2]           ; clock    ;
; N/A           ; None        ; -3.108 ns ; mode[0]   ; int_reg[3]           ; clock    ;
; N/A           ; None        ; -3.108 ns ; mode[0]   ; int_reg[4]           ; clock    ;
; N/A           ; None        ; -3.108 ns ; mode[0]   ; int_reg[5]           ; clock    ;
; N/A           ; None        ; -3.108 ns ; mode[0]   ; int_reg[5]~DUPLICATE ; clock    ;
; N/A           ; None        ; -3.156 ns ; mode[1]   ; int_reg[1]           ; clock    ;
; N/A           ; None        ; -3.156 ns ; mode[1]   ; int_reg[6]~DUPLICATE ; clock    ;
; N/A           ; None        ; -3.156 ns ; mode[1]   ; int_reg[7]           ; clock    ;
; N/A           ; None        ; -3.156 ns ; mode[1]   ; int_reg[6]           ; clock    ;
; N/A           ; None        ; -3.469 ns ; datain[1] ; int_reg[1]           ; clock    ;
+---------------+-------------+-----------+-----------+----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Sun Dec 07 12:32:04 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off reg8 -c reg8 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 500.0 MHz between source register "int_reg[0]" and destination register "int_reg[6]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.476 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y4_N1; Fanout = 5; REG Node = 'int_reg[0]'
            Info: 2: + IC(0.255 ns) + CELL(0.309 ns) = 0.564 ns; Loc. = LCCOMB_X31_Y4_N16; Fanout = 2; COMB Node = 'Add0~250'
            Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.599 ns; Loc. = LCCOMB_X31_Y4_N18; Fanout = 2; COMB Node = 'Add0~254'
            Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 0.634 ns; Loc. = LCCOMB_X31_Y4_N20; Fanout = 2; COMB Node = 'Add0~258'
            Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 0.669 ns; Loc. = LCCOMB_X31_Y4_N22; Fanout = 2; COMB Node = 'Add0~262'
            Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 0.704 ns; Loc. = LCCOMB_X31_Y4_N24; Fanout = 2; COMB Node = 'Add0~266'
            Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 0.739 ns; Loc. = LCCOMB_X31_Y4_N26; Fanout = 2; COMB Node = 'Add0~270'
            Info: 8: + IC(0.000 ns) + CELL(0.125 ns) = 0.864 ns; Loc. = LCCOMB_X31_Y4_N28; Fanout = 2; COMB Node = 'Add0~273'
            Info: 9: + IC(0.404 ns) + CELL(0.053 ns) = 1.321 ns; Loc. = LCCOMB_X31_Y4_N4; Fanout = 1; COMB Node = 'Mux1~17'
            Info: 10: + IC(0.000 ns) + CELL(0.155 ns) = 1.476 ns; Loc. = LCFF_X31_Y4_N5; Fanout = 5; REG Node = 'int_reg[6]'
            Info: Total cell delay = 0.817 ns ( 55.35 % )
            Info: Total interconnect delay = 0.659 ns ( 44.65 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.484 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X31_Y4_N5; Fanout = 5; REG Node = 'int_reg[6]'
                Info: Total cell delay = 1.472 ns ( 59.26 % )
                Info: Total interconnect delay = 1.012 ns ( 40.74 % )
            Info: - Longest clock path from clock "clock" to source register is 2.484 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X31_Y4_N1; Fanout = 5; REG Node = 'int_reg[0]'
                Info: Total cell delay = 1.472 ns ( 59.26 % )
                Info: Total interconnect delay = 1.012 ns ( 40.74 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "int_reg[3]" (data pin = "mode[2]", clock pin = "clock") is 3.782 ns
    Info: + Longest pin to register delay is 6.173 ns
        Info: 1: + IC(0.000 ns) + CELL(0.847 ns) = 0.847 ns; Loc. = PIN_Y8; Fanout = 3; PIN Node = 'mode[2]'
        Info: 2: + IC(3.835 ns) + CELL(0.366 ns) = 5.048 ns; Loc. = LCCOMB_X30_Y4_N28; Fanout = 10; COMB Node = 'int_reg[0]~132'
        Info: 3: + IC(0.592 ns) + CELL(0.378 ns) = 6.018 ns; Loc. = LCCOMB_X30_Y4_N4; Fanout = 1; COMB Node = 'Mux4~17'
        Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 6.173 ns; Loc. = LCFF_X30_Y4_N5; Fanout = 6; REG Node = 'int_reg[3]'
        Info: Total cell delay = 1.746 ns ( 28.28 % )
        Info: Total interconnect delay = 4.427 ns ( 71.72 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.481 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.666 ns) + CELL(0.618 ns) = 2.481 ns; Loc. = LCFF_X30_Y4_N5; Fanout = 6; REG Node = 'int_reg[3]'
        Info: Total cell delay = 1.472 ns ( 59.33 % )
        Info: Total interconnect delay = 1.009 ns ( 40.67 % )
Info: tco from clock "clock" to destination pin "termcnt" through register "int_reg[6]" is 6.492 ns
    Info: + Longest clock path from clock "clock" to source register is 2.484 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X31_Y4_N5; Fanout = 5; REG Node = 'int_reg[6]'
        Info: Total cell delay = 1.472 ns ( 59.26 % )
        Info: Total interconnect delay = 1.012 ns ( 40.74 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.914 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y4_N5; Fanout = 5; REG Node = 'int_reg[6]'
        Info: 2: + IC(0.560 ns) + CELL(0.228 ns) = 0.788 ns; Loc. = LCCOMB_X30_Y4_N26; Fanout = 1; COMB Node = 'det_zero~38'
        Info: 3: + IC(0.202 ns) + CELL(0.053 ns) = 1.043 ns; Loc. = LCCOMB_X30_Y4_N30; Fanout = 1; COMB Node = 'det_zero~6'
        Info: 4: + IC(0.889 ns) + CELL(1.982 ns) = 3.914 ns; Loc. = PIN_AB7; Fanout = 0; PIN Node = 'termcnt'
        Info: Total cell delay = 2.263 ns ( 57.82 % )
        Info: Total interconnect delay = 1.651 ns ( 42.18 % )
Info: th for register "int_reg[5]" (data pin = "datain[5]", clock pin = "clock") is -2.286 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.481 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.666 ns) + CELL(0.618 ns) = 2.481 ns; Loc. = LCFF_X30_Y4_N21; Fanout = 3; REG Node = 'int_reg[5]'
        Info: Total cell delay = 1.472 ns ( 59.33 % )
        Info: Total interconnect delay = 1.009 ns ( 40.67 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 4.916 ns
        Info: 1: + IC(0.000 ns) + CELL(0.847 ns) = 0.847 ns; Loc. = PIN_Y7; Fanout = 2; PIN Node = 'datain[5]'
        Info: 2: + IC(3.760 ns) + CELL(0.154 ns) = 4.761 ns; Loc. = LCCOMB_X30_Y4_N20; Fanout = 1; COMB Node = 'Mux2~17'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.916 ns; Loc. = LCFF_X30_Y4_N21; Fanout = 3; REG Node = 'int_reg[5]'
        Info: Total cell delay = 1.156 ns ( 23.52 % )
        Info: Total interconnect delay = 3.760 ns ( 76.48 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 133 megabytes of memory during processing
    Info: Processing ended: Sun Dec 07 12:32:05 2008
    Info: Elapsed time: 00:00:01