reg8.fit.rpt

通过VHDL实现4位全加器

; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                              ; Auto                           ; Auto                           ;
; Auto Register Duplication                                             ; Auto                           ; Auto                           ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                          ;
+------------+------------+---------------------------------------------------+--------------------------+-----------+----------------+----------------------+------------------+-----------------------+
; Node       ; Action     ; Operation                                         ; Reason                   ; Node Port ; Node Port Name ; Destination Node     ; Destination Port ; Destination Port Name ;
+------------+------------+---------------------------------------------------+--------------------------+-----------+----------------+----------------------+------------------+-----------------------+
; Mux1~17    ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ;           ;                ; Mux1~17DUPLICATE     ;                  ;                       ;
; Mux2~17    ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ;           ;                ; Mux2~17DUPLICATE     ;                  ;                       ;
; int_reg[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ;           ;                ; int_reg[5]~DUPLICATE ;                  ;                       ;
; int_reg[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ;           ;                ; int_reg[6]~DUPLICATE ;                  ;                       ;
+------------+------------+---------------------------------------------------+--------------------------+-----------+----------------+----------------------+------------------+-----------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/Engineering Document/Quartus7.2/register8/reg8.pin.


+----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                        ;
+----------------------------------------------+-----------------------+
; Resource                                     ; Usage                 ;
+----------------------------------------------+-----------------------+
; ALUTs Used                                   ; 24 / 12,480 ( < 1 % ) ;
; Dedicated logic registers                    ; 10 / 12,480 ( < 1 % ) ;
;                                              ;                       ;
; ALUTs Unavailable                            ; 3                     ;
;     -- Due to unpartnered 7 input function   ; 0                     ;
;     -- Due to unpartnered 6 input function   ; 3                     ;
;                                              ;                       ;
; Combinational ALUT usage by number of inputs ;                       ;
;     -- 7 input functions                     ; 0                     ;
;     -- 6 input functions                     ; 10                    ;
;     -- 5 input functions                     ; 1                     ;
;     -- 4 input functions                     ; 1                     ;
;     -- <=3 input functions                   ; 12                    ;
;                                              ;                       ;
; Combinational ALUTs by mode                  ;                       ;
;     -- normal mode                           ; 16                    ;
;     -- extended LUT mode                     ; 0                     ;
;     -- arithmetic mode                       ; 8                     ;
;     -- shared arithmetic mode                ; 0                     ;
;                                              ;                       ;
; Logic utilization                            ; 27 / 12,480 ( < 1 % ) ;
;     -- ALUT/register pairs used              ; 24                    ;
;         -- Combinational with no register    ; 14                    ;
;         -- Register only                     ; 0                     ;
;         -- Combinational with a register     ; 10                    ;
;     -- ALUT/register pairs unavailable       ; 3                     ;
;                                              ;                       ;
; Total registers*                             ; 10 / 14,410 ( < 1 % ) ;
;     -- Dedicated logic registers             ; 10 / 12,480 ( < 1 % ) ;
;     -- I/O registers                         ; 0 / 1,930 ( 0 % )     ;
;                                              ;                       ;
; ALMs:  partially or completely used          ; 15 / 6,240 ( < 1 % )  ;
;                                              ;                       ;
; Total LABs:  partially or completely used    ; 2 / 780 ( < 1 % )     ;
;                                              ;                       ;
; User inserted logic elements                 ; 0                     ;
; Virtual pins                                 ; 0                     ;
; I/O pins                                     ; 23 / 343 ( 7 % )      ;
;     -- Clock pins                            ; 1 / 16 ( 6 % )        ;
; Global signals                               ; 1                     ;
; M512s                                        ; 0 / 104 ( 0 % )       ;
; M4Ks                                         ; 0 / 78 ( 0 % )        ;
; Total block memory bits                      ; 0 / 419,328 ( 0 % )   ;
; Total block memory implementation bits       ; 0 / 419,328 ( 0 % )   ;
; DSP block 9-bit elements                     ; 0 / 96 ( 0 % )        ;
; PLLs                                         ; 0 / 6 ( 0 % )         ;
; Global clocks                                ; 1 / 16 ( 6 % )        ;
; Regional clocks                              ; 0 / 32 ( 0 % )        ;
; SERDES transmitters                          ; 0 / 38 ( 0 % )        ;
; SERDES receivers                             ; 0 / 42 ( 0 % )        ;
; Average interconnect usage                   ; 0%                    ;
; Peak interconnect usage                      ; 0%                    ;