reg8.fit.rpt

通过VHDL实现4位全加器

Fitter report for reg8
Sun Dec 07 12:31:55 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Netlist Optimizations
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Delay Chain Summary
 14. Pad To Core Delay Chain Fanout
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Interconnect Usage Summary
 19. LAB Logic Elements
 20. LAB-wide Signals
 21. LAB Signals Sourced
 22. LAB Signals Sourced Out
 23. LAB Distinct Inputs
 24. I/O Rules Summary
 25. I/O Rules Details
 26. I/O Rules Matrix
 27. Fitter Device Options
 28. Operating Settings and Conditions
 29. Advanced Data - General
 30. Advanced Data - Placement Preparation
 31. Advanced Data - Placement
 32. Advanced Data - Routing
 33. Fitter Messages
 34. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Fitter Summary                                                          ;
+-------------------------------+-----------------------------------------+
; Fitter Status                 ; Successful - Sun Dec 07 12:31:55 2008   ;
; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name                 ; reg8                                    ;
; Top-level Entity Name         ; reg8                                    ;
; Family                        ; Stratix II                              ;
; Device                        ; EP2S15F484C3                            ;
; Timing Models                 ; Final                                   ;
; Logic utilization             ; < 1 %                                   ;
;     Combinational ALUTs       ; 24 / 12,480 ( < 1 % )                   ;
;     Dedicated logic registers ; 10 / 12,480 ( < 1 % )                   ;
; Total registers               ; 10                                      ;
; Total pins                    ; 23 / 343 ( 7 % )                        ;
; Total virtual pins            ; 0                                       ;
; Total block memory bits       ; 0 / 419,328 ( 0 % )                     ;
; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                          ;
; Total PLLs                    ; 0 / 6 ( 0 % )                           ;
; Total DLLs                    ; 0 / 2 ( 0 % )                           ;
+-------------------------------+-----------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; AUTO                           ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;