reg8.map.summary

通过VHDL实现4位全加器

Analysis & Synthesis Status : Successful - Sun Dec 07 12:31:49 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Web Edition
Revision Name : reg8
Top-level Entity Name : reg8
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 22
    Dedicated logic registers : 8
Total registers : 8
Total pins : 23
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0