reg8.flow.rpt

通过VHDL实现4位全加器

Flow report for reg8
Sun Dec 07 12:32:05 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Flow Summary                                                            ;
+-------------------------------+-----------------------------------------+
; Flow Status                   ; Successful - Sun Dec 07 12:32:05 2008   ;
; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name                 ; reg8                                    ;
; Top-level Entity Name         ; reg8                                    ;
; Family                        ; Stratix II                              ;
; Met timing requirements       ; Yes                                     ;
; Logic utilization             ; < 1 %                                   ;
;     Combinational ALUTs       ; 24 / 12,480 ( < 1 % )                   ;
;     Dedicated logic registers ; 10 / 12,480 ( < 1 % )                   ;
; Total registers               ; 10                                      ;
; Total pins                    ; 23 / 343 ( 7 % )                        ;
; Total virtual pins            ; 0                                       ;
; Total block memory bits       ; 0 / 419,328 ( 0 % )                     ;
; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                          ;
; Total PLLs                    ; 0 / 6 ( 0 % )                           ;
; Total DLLs                    ; 0 / 2 ( 0 % )                           ;
; Device                        ; EP2S15F484C3                            ;
; Timing Models                 ; Final                                   ;
+-------------------------------+-----------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 12/07/2008 12:31:48 ;
; Main task         ; Compilation         ;
; Revision Name     ; reg8                ;
+-------------------+---------------------+


+-----------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                        ;
+------------------------------------+---------+---------------+-------------+------------+
; Assignment Name                    ; Value   ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------+---------------+-------------+------------+
; PARTITION_COLOR                    ; 2147039 ; --            ; --          ; Top        ;
; PARTITION_NETLIST_TYPE             ; SOURCE  ; --            ; --          ; Top        ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off     ; --            ; --          ; eda_palace ;
+------------------------------------+---------+---------------+-------------+------------+


+------------------------------------------------------------------+
; Flow Elapsed Time                                                ;
+-------------------------+--------------+-------------------------+
; Module Name             ; Elapsed Time ; Average Processors Used ;
+-------------------------+--------------+-------------------------+
; Analysis & Synthesis    ; 00:00:02     ; 1.0                     ;
; Fitter                  ; 00:00:04     ; 1.0                     ;
; Assembler               ; 00:00:06     ; 1.0                     ;
; Classic Timing Analyzer ; 00:00:01     ; 1.0                     ;
; Total                   ; 00:00:13     ; --                      ;
+-------------------------+--------------+-------------------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off reg8 -c reg8
quartus_fit --read_settings_files=off --write_settings_files=off reg8 -c reg8
quartus_asm --read_settings_files=off --write_settings_files=off reg8 -c reg8
quartus_tan --read_settings_files=off --write_settings_files=off reg8 -c reg8 --timing_analysis_only