reg8.tan.summary

通过VHDL实现4位全加器

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.782 ns
From           : mode[2]
To             : int_reg[3]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.492 ns
From           : int_reg[6]
To             : termcnt
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.286 ns
From           : datain[5]
To             : int_reg[5]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : int_reg[0]
To             : int_reg[6]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------