count10.vhd

用vhdl编写的十进制计数器

LIBRARY IEEE;                            
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT10 IS
  PORT(CLK:IN STD_LOGIC;                      ----时钟信号
        Y0:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);    ----显示信号
        SLC:buffer STD_LOGIC_VECTOR(2 DOWNTO 0));   ----数码管地址选择信号
END ENTITY COUNT10;
ARCHITECTURE ART OF COUNT10 IS
SIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL P:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL w:STD_LOGIC;
BEGIN
P1:PROCESS(CLK)                           ----十进制计数
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
  IF Q="1001" THEN
    Q<="0000";                            ----清零
  ELSE
  Q<=Q+1;
  END IF;
  if p="110" then
    w<='0';
  elsif p="001" then
    w<='1';
  end if;
end if;
END PROCESS ;
P2:PROCESS(clk)                       ----数码管地址选择计数
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
  IF w='0' THEN
     P<=P-1;
  ELSIF w='1' THEN
     P<=P+1;
  END IF;
END IF;
END PROCESS;
slc<=p;
P4:PROCESS(Q)
BEGIN
CASE Q IS 
   WHEN "0000"=>Y0<="0111111";            ----显示0 
   WHEN "0001"=>Y0<="0000110";            ----显示1
   WHEN "0010"=>Y0<="1011011";            ----显示2
   WHEN "0011"=>Y0<="1001111";            ----显示3
   WHEN "0100"=>Y0<="1100110";            ----显示4
   WHEN "0101"=>Y0<="1101101";            ----显示5
   WHEN "0110"=>Y0<="1111101";            ----显示6
   WHEN "0111"=>Y0<="0000111";            ----显示7
   WHEN "1000"=>Y0<="1111111";            ----显示8
   WHEN "1001"=>Y0<="1101111";            ----显示9
   WHEN OTHERS=>Y0<="0000000";
END CASE;
END PROCESS;
END ARCHITECTURE ART;