📄 clock.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity clock is
port(opt :in std_logic_vector(1 downto 0); --select the one which is wanted to be changed
chg :in std_logic; --use for set time
clkt :in std_logic; --clock for counter
clks :in std_logic; --clock for speeker
hour_low :out std_logic_vector(3 downto 0);
hour_high :out std_logic_vector(3 downto 0);
minute_low:out std_logic_vector(3 downto 0);
minute_high:out std_logic_vector(3 downto 0);
second_low :out std_logic_vector(3 downto 0);
second_high:out std_logic_vector(3 downto 0);
spk :out std_logic);
end clock;
architecture one of clock is
component mux24 is
port(input :in std_logic_vector(1 downto 0);
result:out std_logic_vector(3 downto 0));
end component;
component ctrl is
port(clk :in std_logic;
sel :in std_logic;
set :in std_logic;
clkout :out std_logic);
end component;
component counter is
generic(MAX :integer :=63);
port(clk :in std_logic;
c_low :out std_logic_vector(3 downto 0);
c_high :out std_logic_vector(3 downto 0);
co :out std_logic);
end component;
component speeker is
port(clkin1:in std_logic;
clkin2:in std_logic;
ok :in std_logic;
spkout:out std_logic);
end component;
signal res:std_logic_vector(3 downto 0);
signal carry0,carry1,clk0,clk1,clk2:std_logic;
begin
u1:mux24 port map(input(0)=>opt(0),input(1)=>opt(1),result=>res);
u2:ctrl port map(clk=>clkt ,sel=>res(0),set=>chg,clkout=>clk0); --clock for second
u3:ctrl port map(clk=>carry0,sel=>res(1),set=>chg,clkout=>clk1); --clock for minute
u4:ctrl port map(clk=>carry1,sel=>res(2),set=>chg,clkout=>clk2); --clock for hour
u6:counter generic map(59)
port map(clk=>clk0,c_low=>second_low,c_high=>second_high,co=>carry0);
u7:counter generic map(59)
port map(clk=>clk1,c_low=>minute_low,c_high=>minute_high,co=>carry1);
u8:counter generic map(23)
port map(clk=>clk2,c_low=>hour_low,c_high=>hour_high);
u9:speeker port map(clkin1=>clks,clkin2=>clkt,ok=>carry1,spkout=>spk); --delay for 30 seconds
end one;
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