counter.vhd

来自「用vhdl实现的多功能时钟,有整点响铃,秒表等多种功能」· VHDL 代码 · 共 38 行

library	ieee;
use ieee.std_logic_1164.all;
use	ieee.std_logic_unsigned.all;

entity counter is
generic(MAX	:integer :=60);
port(clk	:in		std_logic;
	 c_low	:out	std_logic_vector(3 downto 0);
	 c_high	:out	std_logic_vector(3 downto 0);
	 co		:out	std_logic);
end counter;

architecture sixty of counter is
signal	counter2:std_logic_vector(5 downto 0);	--extend for counter
signal	c_l,c_h	:std_logic_vector(3 downto 0);
begin
	process(clk)
	begin
	if clk='1' and clk'event
	then  if counter2 < MAX 
		  then  counter2 <= counter2 + '1';
			    if c_l = "1001"					--decade number
			    then  c_l <= "0000";
					  c_h <= c_h+'1';
				elsif c_l < "1001"
				then  c_l <= c_l + '1';
			    end if;
			    co  <= '0';
		  else  counter2 <= "000000";
				c_l	 <= "0000";
				c_h	 <= "0000";
				co	 <= '1';
		  end if;	
	end if;
	end process;
	c_low <= c_l;
	c_high<= c_h;
end sixty;