mux24.vhd

来自「用vhdl实现的多功能时钟,有整点响铃,秒表等多种功能」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;

entity mux24 is
port(input :in  std_logic_vector(1 downto 0);
	 result:out std_logic_vector(3 downto 0));
end mux24;

architecture one of mux24 is
begin
with input select
result <= "1110" when "00" ,
		  "1101" when "01" ,
		  "1011" when "10" ,
		  "0111" when "11" ,
		  "1111" when others;
end one;