speeker.vhd

来自「用vhdl实现的多功能时钟,有整点响铃,秒表等多种功能」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;

entity speeker	is
port(clkin1:in std_logic;
	 clkin2:in std_logic;
	 ok	   :in std_logic;
	 spkout:out std_logic);
end speeker;

architecture entire of speeker is
component counter is
generic(MAX	:integer :=63);
port(clk	:in		std_logic;
	 c_low	:out	std_logic_vector(3 downto 0);
	 c_high	:out	std_logic_vector(3 downto 0);
	 co		:out	std_logic);
end component;
signal carry,start:std_logic;
begin
process(ok,carry)
	begin
	if carry = '1'
	then start <= '0';
	elsif ok='1' and ok'event 
	then start <= '1';
	end if;
end process;
u1:counter  generic map(30)
			port map(clk=>clkin2,co=>carry);
spkout<= start and clkin1;
end entire;