float.map.summary

来自「该文档是基于QUARTUS2_6.0的Verilog试验例程」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Thu Nov 15 16:42:00 2007
Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
Revision Name : float
Top-level Entity Name : float
Family : Cyclone
Total logic elements : 17
Total pins : 25
Total virtual pins : 0
Total memory bits : 1,024
Total PLLs : 0