float.tan.summary

该文档是基于QUARTUS2_6.0的Verilog试验例程

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.753 ns
From           : clr
To             : shj:inst7|data2[5]
From Clock     : --
To Clock       : clkx
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.555 ns
From           : zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg5
To             : out[10]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.333 ns
From           : control
To             : shj:inst7|data2[1]
From Clock     : --
To Clock       : clkx
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 249.94 MHz ( period = 4.001 ns )
From           : saomiao:inst|data0[0]
To             : zimo:inst4|altsyncram:altsyncram_component|altsyncram_d651:auto_generated|ram_block1a15~porta_address_reg4
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clkx'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : shj:inst7|data2[0]
To             : shj:inst7|data2[5]
From Clock     : clkx
To Clock       : clkx
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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