paobiao.map.summary

来自「该文档是基于QUARTUS2_6.0的Verilog试验例程」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Sun Dec 02 15:07:38 2007
Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
Revision Name : paobiao
Top-level Entity Name : paobiao
Family : Cyclone
Total logic elements : 129
Total pins : 14
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0