saomiao.v

来自「该文档是基于QUARTUS2_6.0的Verilog试验例程」· Verilog 代码 · 共 23 行

module saomiao(clk,cel);
input clk;
output[3:0] cel;
reg[3:0] cel;
reg[15:0] clkx;
reg mm;

always @(posedge clk)
begin        
    clkx=clkx+1;
end

always @(clkx[9:8])
begin
  case(clkx[9:8])
    0:cel=4'b0001;
    1:cel=4'b0010;
    2:cel=4'b0100;
    3:cel=4'b1000;
    default:cel=4'bx;
   endcase
end
endmodule