paobiao.hier_info

该文档是基于QUARTUS2_6.0的Verilog试验例程

|paobiao
q_out[0] <= yima:inst4.out[0]
q_out[1] <= yima:inst4.out[1]
q_out[2] <= yima:inst4.out[2]
q_out[3] <= yima:inst4.out[3]
q_out[4] <= yima:inst4.out[4]
q_out[5] <= yima:inst4.out[5]
q_out[6] <= yima:inst4.out[6]
clk => second:inst2.clk
clk => saomiao:inst1.clk
clr => second:inst2.clr
clr => minute:inst.clr
pause => second:inst2.pause
weikong[0] <= saomiao:inst1.cel[0]
weikong[1] <= saomiao:inst1.cel[1]
weikong[2] <= saomiao:inst1.cel[2]
weikong[3] <= saomiao:inst1.cel[3]


|paobiao|yima:inst4
in[0] => Decoder0.IN3
in[1] => Decoder0.IN2
in[2] => Decoder0.IN1
in[3] => Decoder0.IN0
out[0] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= WideOr7.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE


|paobiao|select:inst5
sel_1[0] => Decoder0.IN3
sel_1[1] => Decoder0.IN2
sel_1[2] => Decoder0.IN1
sel_1[3] => Decoder0.IN0
msl_1[0] => Selector3.IN6
msl_1[1] => Selector2.IN6
msl_1[2] => Selector1.IN6
msl_1[3] => Selector0.IN6
msh_1[0] => Selector3.IN7
msh_1[1] => Selector2.IN7
msh_1[2] => Selector1.IN7
msh_1[3] => Selector0.IN7
sl_1[0] => Selector3.IN8
sl_1[1] => Selector2.IN8
sl_1[2] => Selector1.IN8
sl_1[3] => Selector0.IN8
sh_1[0] => Selector3.IN9
sh_1[1] => Selector2.IN9
sh_1[2] => Selector1.IN9
sh_1[3] => Selector0.IN9
out_data[0] <= Selector3.DB_MAX_OUTPUT_PORT_TYPE
out_data[1] <= Selector2.DB_MAX_OUTPUT_PORT_TYPE
out_data[2] <= Selector1.DB_MAX_OUTPUT_PORT_TYPE
out_data[3] <= Selector0.DB_MAX_OUTPUT_PORT_TYPE


|paobiao|minute:inst
cn => msl[2]~reg0.CLK
cn => msl[1]~reg0.CLK
cn => msl[0]~reg0.CLK
cn => msh[3]~reg0.CLK
cn => msh[2]~reg0.CLK
cn => msh[1]~reg0.CLK
cn => msh[0]~reg0.CLK
cn => msl[3]~reg0.CLK
clr => msl[2]~reg0.ACLR
clr => msl[1]~reg0.ACLR
clr => msl[0]~reg0.ACLR
clr => msh[3]~reg0.ACLR
clr => msh[2]~reg0.ACLR
clr => msh[1]~reg0.ACLR
clr => msh[0]~reg0.ACLR
clr => msl[3]~reg0.ACLR
msl[0] <= msl[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
msl[1] <= msl[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
msl[2] <= msl[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
msl[3] <= msl[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
msh[0] <= msh[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
msh[1] <= msh[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
msh[2] <= msh[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
msh[3] <= msh[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|paobiao|second:inst2
clk => rr[29].CLK
clk => rr[28].CLK
clk => rr[27].CLK
clk => rr[26].CLK
clk => rr[25].CLK
clk => rr[24].CLK
clk => rr[23].CLK
clk => rr[22].CLK
clk => rr[21].CLK
clk => rr[20].CLK
clk => rr[19].CLK
clk => rr[18].CLK
clk => rr[17].CLK
clk => rr[16].CLK
clk => rr[15].CLK
clk => rr[14].CLK
clk => rr[13].CLK
clk => rr[12].CLK
clk => rr[11].CLK
clk => rr[10].CLK
clk => rr[9].CLK
clk => rr[8].CLK
clk => rr[7].CLK
clk => rr[6].CLK
clk => rr[5].CLK
clk => rr[4].CLK
clk => rr[3].CLK
clk => rr[2].CLK
clk => rr[1].CLK
clk => rr[0].CLK
clk => clk_1.CLK
clk => rr[30].CLK
clr => sl~8.OUTPUTSELECT
clr => sl~9.OUTPUTSELECT
clr => sl~10.OUTPUTSELECT
clr => sl~11.OUTPUTSELECT
clr => sh~12.OUTPUTSELECT
clr => sh~13.OUTPUTSELECT
clr => sh~14.OUTPUTSELECT
clr => sh~15.OUTPUTSELECT
clr => cn~3.OUTPUTSELECT
pause => sl~4.OUTPUTSELECT
pause => sl~5.OUTPUTSELECT
pause => sl~6.OUTPUTSELECT
pause => sl~7.OUTPUTSELECT
pause => sh~8.OUTPUTSELECT
pause => sh~9.OUTPUTSELECT
pause => sh~10.OUTPUTSELECT
pause => sh~11.OUTPUTSELECT
pause => cn~2.OUTPUTSELECT
sl[0] <= sl[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sl[1] <= sl[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sl[2] <= sl[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sl[3] <= sl[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sh[0] <= sh[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sh[1] <= sh[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sh[2] <= sh[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sh[3] <= sh[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cn <= cn~reg0.DB_MAX_OUTPUT_PORT_TYPE


|paobiao|saomiao:inst1
clk => clkx[14].CLK
clk => clkx[13].CLK
clk => clkx[12].CLK
clk => clkx[11].CLK
clk => clkx[10].CLK
clk => clkx[9].CLK
clk => clkx[8].CLK
clk => clkx[7].CLK
clk => clkx[6].CLK
clk => clkx[5].CLK
clk => clkx[4].CLK
clk => clkx[3].CLK
clk => clkx[2].CLK
clk => clkx[1].CLK
clk => clkx[0].CLK
clk => clkx[15].CLK
cel[0] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
cel[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
cel[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
cel[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE