add.map.summary

来自「该文档是基于QUARTUS2_6.0的Verilog试验例程」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Sun Nov 11 10:06:18 2007
Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
Revision Name : add
Top-level Entity Name : add
Family : Cyclone
Total logic elements : 2
Total pins : 4
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0