control.vhd

for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION

-- ============================================================
-- File Name: control.vhd
-- ============================================================

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY control IS 
	PORT
	(
		clk		: IN STD_LOGIC;
		rst		: IN STD_LOGIC;
		din		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		ld_x	: OUT STD_LOGIC;
		ld_y	: OUT STD_LOGIC;
		aludr	: OUT STD_LOGIC;
		funct	: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
		memdr	: OUT STD_LOGIC;
		wr		: OUT STD_LOGIC;
		addr	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END control;

ARCHITECTURE behavior OF control IS

	TYPE ctrl_state IS (S0, S1, S2, S3, S4, S5);
	SIGNAL state	: ctrl_state;
	SIGNAL addr_int	: INTEGER := 0;
	SIGNAL r_funct	: STD_LOGIC_VECTOR (2 DOWNTO 0);

BEGIN

	funct <= r_funct;
	addr <= CONV_STD_LOGIC_VECTOR(addr_int, 8);
	
	PROCESS (din)
		VARIABLE v_funct : INTEGER;
	BEGIN
		v_funct := CONV_INTEGER(din AND "00000111");
		r_funct <= CONV_STD_LOGIC_VECTOR(v_funct, 3);
	END PROCESS;

	PROCESS (clk, rst)
	BEGIN
		IF (rst = '1') THEN
			addr_int <= 0;
			memdr <= '0';
			wr <= '0';
			ld_x <= '0';
			ld_y <= '0';
			aludr <= '0';
			state <= S0;
		ELSIF (clk'EVENT AND clk = '0') THEN	--at negative-edge of clock, send the command signals
			CASE state IS
				WHEN S0 =>	memdr <= '1';	
							wr <= '0';
							ld_x <= '1';
							ld_y <= '0';
							aludr <= '0';
							state <= S1;
				WHEN S1 =>	addr_int <= addr_int + 1;
							memdr <= '1';	
							wr <= '0';
							ld_x <= '0';
							ld_y <= '1';
							aludr <= '0';
							state <= S2;
				WHEN S2 =>	addr_int <= addr_int + 1;
							memdr <= '1';	
							wr <= '0';
							ld_x <= '0';
							ld_y <= '0';
							aludr <= '0';
							state <= S3;
				WHEN S3 =>	addr_int <= addr_int - 2;
							memdr <= '1';	
							wr <= '1';
							ld_x <= '0';
							ld_y <= '0';
							aludr <= '1';
							state <= S4;
				WHEN S4 =>	addr_int <= addr_int + 3;
							memdr <= '1';	
							wr <= '0';
							ld_x <= '1';
							ld_y <= '0';
							aludr <= '0';
							IF (addr_int + 3 < 255) THEN
								state <= S1;
							ELSE
								state <= S5;
							END IF;
				WHEN S5 =>	memdr <= '0';
							aludr <= '0';
			END CASE;
		END IF;
	END PROCESS;

END behavior;